1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 4 */ 5 6 #ifndef _UNIPRO_H_ 7 #define _UNIPRO_H_ 8 9 /* 10 * M-TX Configuration Attributes 11 */ 12 #define TX_HIBERN8TIME_CAPABILITY 0x000F 13 #define TX_MODE 0x0021 14 #define TX_HSRATE_SERIES 0x0022 15 #define TX_HSGEAR 0x0023 16 #define TX_PWMGEAR 0x0024 17 #define TX_AMPLITUDE 0x0025 18 #define TX_HS_SLEWRATE 0x0026 19 #define TX_SYNC_SOURCE 0x0027 20 #define TX_HS_SYNC_LENGTH 0x0028 21 #define TX_HS_PREPARE_LENGTH 0x0029 22 #define TX_LS_PREPARE_LENGTH 0x002A 23 #define TX_HIBERN8_CONTROL 0x002B 24 #define TX_LCC_ENABLE 0x002C 25 #define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D 26 #define TX_BYPASS_8B10B_ENABLE 0x002E 27 #define TX_DRIVER_POLARITY 0x002F 28 #define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030 29 #define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031 30 #define TX_LCC_SEQUENCER 0x0032 31 #define TX_MIN_ACTIVATETIME 0x0033 32 #define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 33 #define TX_REFCLKFREQ 0x00EB 34 #define TX_CFGCLKFREQVAL 0x00EC 35 #define CFGEXTRATTR 0x00F0 36 #define DITHERCTRL2 0x00F1 37 38 /* 39 * M-RX Configuration Attributes 40 */ 41 #define RX_MODE 0x00A1 42 #define RX_HSRATE_SERIES 0x00A2 43 #define RX_HSGEAR 0x00A3 44 #define RX_PWMGEAR 0x00A4 45 #define RX_LS_TERMINATED_ENABLE 0x00A5 46 #define RX_HS_UNTERMINATED_ENABLE 0x00A6 47 #define RX_ENTER_HIBERN8 0x00A7 48 #define RX_BYPASS_8B10B_ENABLE 0x00A8 49 #define RX_TERMINATION_FORCE_ENABLE 0x00A9 50 #define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F 51 #define RX_HIBERN8TIME_CAPABILITY 0x0092 52 #define RX_REFCLKFREQ 0x00EB 53 #define RX_CFGCLKFREQVAL 0x00EC 54 #define CFGWIDEINLN 0x00F0 55 #define CFGRXCDR8 0x00BA 56 #define ENARXDIRECTCFG4 0x00F2 57 #define CFGRXOVR8 0x00BD 58 #define RXDIRECTCTRL2 0x00C7 59 #define ENARXDIRECTCFG3 0x00F3 60 #define RXCALCTRL 0x00B4 61 #define ENARXDIRECTCFG2 0x00F4 62 #define CFGRXOVR4 0x00E9 63 #define RXSQCTRL 0x00B5 64 #define CFGRXOVR6 0x00BF 65 #define RX_HS_G1_SYNC_LENGTH_CAP 0x008B 66 #define RX_HS_G1_PREP_LENGTH_CAP 0x008C 67 #define RX_HS_G2_SYNC_LENGTH_CAP 0x0094 68 #define RX_HS_G3_SYNC_LENGTH_CAP 0x0095 69 #define RX_HS_G2_PREP_LENGTH_CAP 0x0096 70 #define RX_HS_G3_PREP_LENGTH_CAP 0x0097 71 #define RX_ADV_GRANULARITY_CAP 0x0098 72 #define RX_MIN_ACTIVATETIME_CAP 0x008F 73 #define RX_HIBERN8TIME_CAP 0x0092 74 #define RX_ADV_HIBERN8TIME_CAP 0x0099 75 #define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A 76 77 78 #define is_mphy_tx_attr(attr) (attr < RX_MODE) 79 #define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) 80 #define SYNC_LEN_FINE(x) ((x) & 0x3F) 81 #define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F)) 82 #define PREP_LEN(x) ((x) & 0xF) 83 84 #define RX_MIN_ACTIVATETIME_UNIT_US 100 85 #define HIBERN8TIME_UNIT_US 100 86 87 /* 88 * Common Block Attributes 89 */ 90 #define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B) 91 #define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF) 92 #define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD) 93 #define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6) 94 #define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA) 95 #define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0) 96 #define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1) 97 #define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3) 98 #define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8) 99 #define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB) 100 101 #define UNIPRO_CB_OFFSET(x) (0x8000 | x) 102 103 /* 104 * PHY Adapter attributes 105 */ 106 #define PA_ACTIVETXDATALANES 0x1560 107 #define PA_ACTIVERXDATALANES 0x1580 108 #define PA_TXTRAILINGCLOCKS 0x1564 109 #define PA_PHY_TYPE 0x1500 110 #define PA_AVAILTXDATALANES 0x1520 111 #define PA_AVAILRXDATALANES 0x1540 112 #define PA_MINRXTRAILINGCLOCKS 0x1543 113 #define PA_TXPWRSTATUS 0x1567 114 #define PA_RXPWRSTATUS 0x1582 115 #define PA_TXFORCECLOCK 0x1562 116 #define PA_TXPWRMODE 0x1563 117 #define PA_LEGACYDPHYESCDL 0x1570 118 #define PA_MAXTXSPEEDFAST 0x1521 119 #define PA_MAXTXSPEEDSLOW 0x1522 120 #define PA_MAXRXSPEEDFAST 0x1541 121 #define PA_MAXRXSPEEDSLOW 0x1542 122 #define PA_TXLINKSTARTUPHS 0x1544 123 #define PA_LOCAL_TX_LCC_ENABLE 0x155E 124 #define PA_TXSPEEDFAST 0x1565 125 #define PA_TXSPEEDSLOW 0x1566 126 #define PA_REMOTEVERINFO 0x15A0 127 #define PA_TXGEAR 0x1568 128 #define PA_TXTERMINATION 0x1569 129 #define PA_HSSERIES 0x156A 130 #define PA_PWRMODE 0x1571 131 #define PA_RXGEAR 0x1583 132 #define PA_RXTERMINATION 0x1584 133 #define PA_MAXRXPWMGEAR 0x1586 134 #define PA_MAXRXHSGEAR 0x1587 135 #define PA_RXHSUNTERMCAP 0x15A5 136 #define PA_RXLSTERMCAP 0x15A6 137 #define PA_GRANULARITY 0x15AA 138 #define PA_PACPREQTIMEOUT 0x1590 139 #define PA_PACPREQEOBTIMEOUT 0x1591 140 #define PA_HIBERN8TIME 0x15A7 141 #define PA_LOCALVERINFO 0x15A9 142 #define PA_GRANULARITY 0x15AA 143 #define PA_TACTIVATE 0x15A8 144 #define PA_PACPFRAMECOUNT 0x15C0 145 #define PA_PACPERRORCOUNT 0x15C1 146 #define PA_PHYTESTCONTROL 0x15C2 147 #define PA_PWRMODEUSERDATA0 0x15B0 148 #define PA_PWRMODEUSERDATA1 0x15B1 149 #define PA_PWRMODEUSERDATA2 0x15B2 150 #define PA_PWRMODEUSERDATA3 0x15B3 151 #define PA_PWRMODEUSERDATA4 0x15B4 152 #define PA_PWRMODEUSERDATA5 0x15B5 153 #define PA_PWRMODEUSERDATA6 0x15B6 154 #define PA_PWRMODEUSERDATA7 0x15B7 155 #define PA_PWRMODEUSERDATA8 0x15B8 156 #define PA_PWRMODEUSERDATA9 0x15B9 157 #define PA_PWRMODEUSERDATA10 0x15BA 158 #define PA_PWRMODEUSERDATA11 0x15BB 159 #define PA_CONNECTEDTXDATALANES 0x1561 160 #define PA_CONNECTEDRXDATALANES 0x1581 161 #define PA_LOGICALLANEMAP 0x15A1 162 #define PA_SLEEPNOCONFIGTIME 0x15A2 163 #define PA_STALLNOCONFIGTIME 0x15A3 164 #define PA_SAVECONFIGTIME 0x15A4 165 #define PA_TXHSADAPTTYPE 0x15D4 166 167 /* Adpat type for PA_TXHSADAPTTYPE attribute */ 168 #define PA_REFRESH_ADAPT 0x00 169 #define PA_INITIAL_ADAPT 0x01 170 #define PA_NO_ADAPT 0x03 171 172 #define PA_TACTIVATE_TIME_UNIT_US 10 173 #define PA_HIBERN8_TIME_UNIT_US 100 174 175 /*Other attributes*/ 176 #define VS_MPHYCFGUPDT 0xD085 177 #define VS_DEBUGOMC 0xD09E 178 #define VS_POWERSTATE 0xD083 179 180 #define PA_GRANULARITY_MIN_VAL 1 181 #define PA_GRANULARITY_MAX_VAL 6 182 183 /* PHY Adapter Protocol Constants */ 184 #define PA_MAXDATALANES 4 185 186 #define DL_FC0ProtectionTimeOutVal_Default 8191 187 #define DL_TC0ReplayTimeOutVal_Default 65535 188 #define DL_AFC0ReqTimeOutVal_Default 32767 189 #define DL_FC1ProtectionTimeOutVal_Default 8191 190 #define DL_TC1ReplayTimeOutVal_Default 65535 191 #define DL_AFC1ReqTimeOutVal_Default 32767 192 193 #define DME_LocalFC0ProtectionTimeOutVal 0xD041 194 #define DME_LocalTC0ReplayTimeOutVal 0xD042 195 #define DME_LocalAFC0ReqTimeOutVal 0xD043 196 197 /* PA power modes */ 198 enum { 199 FAST_MODE = 1, 200 SLOW_MODE = 2, 201 FASTAUTO_MODE = 4, 202 SLOWAUTO_MODE = 5, 203 UNCHANGED = 7, 204 }; 205 206 #define PWRMODE_MASK 0xF 207 #define PWRMODE_RX_OFFSET 4 208 209 /* PA TX/RX Frequency Series */ 210 enum { 211 PA_HS_MODE_A = 1, 212 PA_HS_MODE_B = 2, 213 }; 214 215 enum ufs_pwm_gear_tag { 216 UFS_PWM_DONT_CHANGE, /* Don't change Gear */ 217 UFS_PWM_G1, /* PWM Gear 1 (default for reset) */ 218 UFS_PWM_G2, /* PWM Gear 2 */ 219 UFS_PWM_G3, /* PWM Gear 3 */ 220 UFS_PWM_G4, /* PWM Gear 4 */ 221 UFS_PWM_G5, /* PWM Gear 5 */ 222 UFS_PWM_G6, /* PWM Gear 6 */ 223 UFS_PWM_G7, /* PWM Gear 7 */ 224 }; 225 226 enum ufs_hs_gear_tag { 227 UFS_HS_DONT_CHANGE, /* Don't change Gear */ 228 UFS_HS_G1, /* HS Gear 1 (default for reset) */ 229 UFS_HS_G2, /* HS Gear 2 */ 230 UFS_HS_G3, /* HS Gear 3 */ 231 UFS_HS_G4, /* HS Gear 4 */ 232 }; 233 234 enum ufs_unipro_ver { 235 UFS_UNIPRO_VER_RESERVED = 0, 236 UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ 237 UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ 238 UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ 239 UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */ 240 UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */ 241 UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */ 242 /* UniPro version field mask in PA_LOCALVERINFO */ 243 UFS_UNIPRO_VER_MASK = 0xF, 244 }; 245 246 /* 247 * Data Link Layer Attributes 248 */ 249 #define DL_TC0TXFCTHRESHOLD 0x2040 250 #define DL_FC0PROTTIMEOUTVAL 0x2041 251 #define DL_TC0REPLAYTIMEOUTVAL 0x2042 252 #define DL_AFC0REQTIMEOUTVAL 0x2043 253 #define DL_AFC0CREDITTHRESHOLD 0x2044 254 #define DL_TC0OUTACKTHRESHOLD 0x2045 255 #define DL_TC1TXFCTHRESHOLD 0x2060 256 #define DL_FC1PROTTIMEOUTVAL 0x2061 257 #define DL_TC1REPLAYTIMEOUTVAL 0x2062 258 #define DL_AFC1REQTIMEOUTVAL 0x2063 259 #define DL_AFC1CREDITTHRESHOLD 0x2064 260 #define DL_TC1OUTACKTHRESHOLD 0x2065 261 #define DL_TXPREEMPTIONCAP 0x2000 262 #define DL_TC0TXMAXSDUSIZE 0x2001 263 #define DL_TC0RXINITCREDITVAL 0x2002 264 #define DL_TC0TXBUFFERSIZE 0x2005 265 #define DL_PEERTC0PRESENT 0x2046 266 #define DL_PEERTC0RXINITCREVAL 0x2047 267 #define DL_TC1TXMAXSDUSIZE 0x2003 268 #define DL_TC1RXINITCREDITVAL 0x2004 269 #define DL_TC1TXBUFFERSIZE 0x2006 270 #define DL_PEERTC1PRESENT 0x2066 271 #define DL_PEERTC1RXINITCREVAL 0x2067 272 273 /* 274 * Network Layer Attributes 275 */ 276 #define N_DEVICEID 0x3000 277 #define N_DEVICEID_VALID 0x3001 278 #define N_TC0TXMAXSDUSIZE 0x3020 279 #define N_TC1TXMAXSDUSIZE 0x3021 280 281 /* 282 * Transport Layer Attributes 283 */ 284 #define T_NUMCPORTS 0x4000 285 #define T_NUMTESTFEATURES 0x4001 286 #define T_CONNECTIONSTATE 0x4020 287 #define T_PEERDEVICEID 0x4021 288 #define T_PEERCPORTID 0x4022 289 #define T_TRAFFICCLASS 0x4023 290 #define T_PROTOCOLID 0x4024 291 #define T_CPORTFLAGS 0x4025 292 #define T_TXTOKENVALUE 0x4026 293 #define T_RXTOKENVALUE 0x4027 294 #define T_LOCALBUFFERSPACE 0x4028 295 #define T_PEERBUFFERSPACE 0x4029 296 #define T_CREDITSTOSEND 0x402A 297 #define T_CPORTMODE 0x402B 298 #define T_TC0TXMAXSDUSIZE 0x4060 299 #define T_TC1TXMAXSDUSIZE 0x4061 300 301 /* CPort setting */ 302 #define E2EFC_ON (1 << 0) 303 #define E2EFC_OFF (0 << 0) 304 #define CSD_N_ON (0 << 1) 305 #define CSD_N_OFF (1 << 1) 306 #define CSV_N_ON (0 << 2) 307 #define CSV_N_OFF (1 << 2) 308 #define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF) 309 310 /* CPort connection state */ 311 enum { 312 CPORT_IDLE = 0, 313 CPORT_CONNECTED, 314 }; 315 316 #endif /* _UNIPRO_H_ */ 317