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Searched refs:PA_CL_UCP_0_W__DATA_REGISTER_MASK (Results 1 – 11 of 11) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5670 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffffL macro
Dgfx_7_2_sh_mask.h5617 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff macro
Dgfx_8_0_sh_mask.h6405 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff macro
Dgfx_8_1_sh_mask.h6939 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h15469 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … macro
Dgc_9_1_sh_mask.h16778 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … macro
Dgc_9_2_1_sh_mask.h16650 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … macro
Dgc_9_4_2_sh_mask.h8899 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … macro
Dgc_11_0_0_sh_mask.h20563 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … macro
Dgc_10_1_0_sh_mask.h22848 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … macro
Dgc_10_3_0_sh_mask.h21025 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK … macro