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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT (Results 1 – 11 of 11) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5583 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000 macro
Dgfx_7_2_sh_mask.h5566 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 macro
Dgfx_8_0_sh_mask.h6354 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 macro
Dgfx_8_1_sh_mask.h6888 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h16889 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … macro
Dgc_9_1_sh_mask.h18198 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … macro
Dgc_9_2_1_sh_mask.h18073 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … macro
Dgc_9_4_2_sh_mask.h10320 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … macro
Dgc_11_0_0_sh_mask.h22088 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … macro
Dgc_10_1_0_sh_mask.h24261 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … macro
Dgc_10_3_0_sh_mask.h22519 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT … macro