1 // SPDX-License-Identifier: (GPL-2.0)
2 /*
3 * oxnas SoC reset driver
4 * based on:
5 * Microsemi MIPS SoC reset driver
6 * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
7 *
8 * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
9 * Copyright (c) 2017 Microsemi Corporation
10 * Copyright (c) 2020 Daniel Golle <daniel@makrotopia.org>
11 */
12 #include <linux/delay.h>
13 #include <linux/io.h>
14 #include <linux/notifier.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/reboot.h>
20 #include <linux/regmap.h>
21
22 /* bit numbers of reset control register */
23 #define OX820_SYS_CTRL_RST_SCU 0
24 #define OX820_SYS_CTRL_RST_COPRO 1
25 #define OX820_SYS_CTRL_RST_ARM0 2
26 #define OX820_SYS_CTRL_RST_ARM1 3
27 #define OX820_SYS_CTRL_RST_USBHS 4
28 #define OX820_SYS_CTRL_RST_USBHSPHYA 5
29 #define OX820_SYS_CTRL_RST_MACA 6
30 #define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA
31 #define OX820_SYS_CTRL_RST_PCIEA 7
32 #define OX820_SYS_CTRL_RST_SGDMA 8
33 #define OX820_SYS_CTRL_RST_CIPHER 9
34 #define OX820_SYS_CTRL_RST_DDR 10
35 #define OX820_SYS_CTRL_RST_SATA 11
36 #define OX820_SYS_CTRL_RST_SATA_LINK 12
37 #define OX820_SYS_CTRL_RST_SATA_PHY 13
38 #define OX820_SYS_CTRL_RST_PCIEPHY 14
39 #define OX820_SYS_CTRL_RST_STATIC 15
40 #define OX820_SYS_CTRL_RST_GPIO 16
41 #define OX820_SYS_CTRL_RST_UART1 17
42 #define OX820_SYS_CTRL_RST_UART2 18
43 #define OX820_SYS_CTRL_RST_MISC 19
44 #define OX820_SYS_CTRL_RST_I2S 20
45 #define OX820_SYS_CTRL_RST_SD 21
46 #define OX820_SYS_CTRL_RST_MACB 22
47 #define OX820_SYS_CTRL_RST_PCIEB 23
48 #define OX820_SYS_CTRL_RST_VIDEO 24
49 #define OX820_SYS_CTRL_RST_DDR_PHY 25
50 #define OX820_SYS_CTRL_RST_USBHSPHYB 26
51 #define OX820_SYS_CTRL_RST_USBDEV 27
52 #define OX820_SYS_CTRL_RST_ARMDBG 29
53 #define OX820_SYS_CTRL_RST_PLLA 30
54 #define OX820_SYS_CTRL_RST_PLLB 31
55
56 /* bit numbers of clock control register */
57 #define OX820_SYS_CTRL_CLK_COPRO 0
58 #define OX820_SYS_CTRL_CLK_DMA 1
59 #define OX820_SYS_CTRL_CLK_CIPHER 2
60 #define OX820_SYS_CTRL_CLK_SD 3
61 #define OX820_SYS_CTRL_CLK_SATA 4
62 #define OX820_SYS_CTRL_CLK_I2S 5
63 #define OX820_SYS_CTRL_CLK_USBHS 6
64 #define OX820_SYS_CTRL_CLK_MACA 7
65 #define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA
66 #define OX820_SYS_CTRL_CLK_PCIEA 8
67 #define OX820_SYS_CTRL_CLK_STATIC 9
68 #define OX820_SYS_CTRL_CLK_MACB 10
69 #define OX820_SYS_CTRL_CLK_PCIEB 11
70 #define OX820_SYS_CTRL_CLK_REF600 12
71 #define OX820_SYS_CTRL_CLK_USBDEV 13
72 #define OX820_SYS_CTRL_CLK_DDR 14
73 #define OX820_SYS_CTRL_CLK_DDRPHY 15
74 #define OX820_SYS_CTRL_CLK_DDRCK 16
75
76 /* Regmap offsets */
77 #define OX820_CLK_SET_REGOFFSET 0x2c
78 #define OX820_CLK_CLR_REGOFFSET 0x30
79 #define OX820_RST_SET_REGOFFSET 0x34
80 #define OX820_RST_CLR_REGOFFSET 0x38
81 #define OX820_SECONDARY_SEL_REGOFFSET 0x14
82 #define OX820_TERTIARY_SEL_REGOFFSET 0x8c
83 #define OX820_QUATERNARY_SEL_REGOFFSET 0x94
84 #define OX820_DEBUG_SEL_REGOFFSET 0x9c
85 #define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4
86 #define OX820_PULLUP_SEL_REGOFFSET 0xac
87 #define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014
88 #define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c
89 #define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094
90 #define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c
91 #define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
92 #define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac
93
94 struct oxnas_restart_context {
95 struct regmap *sys_ctrl;
96 struct notifier_block restart_handler;
97 };
98
ox820_restart_handle(struct notifier_block * this,unsigned long mode,void * cmd)99 static int ox820_restart_handle(struct notifier_block *this,
100 unsigned long mode, void *cmd)
101 {
102 struct oxnas_restart_context *ctx = container_of(this, struct
103 oxnas_restart_context,
104 restart_handler);
105 u32 value;
106
107 /*
108 * Assert reset to cores as per power on defaults
109 * Don't touch the DDR interface as things will come to an impromptu
110 * stop NB Possibly should be asserting reset for PLLB, but there are
111 * timing concerns here according to the docs
112 */
113 value = BIT(OX820_SYS_CTRL_RST_COPRO) |
114 BIT(OX820_SYS_CTRL_RST_USBHS) |
115 BIT(OX820_SYS_CTRL_RST_USBHSPHYA) |
116 BIT(OX820_SYS_CTRL_RST_MACA) |
117 BIT(OX820_SYS_CTRL_RST_PCIEA) |
118 BIT(OX820_SYS_CTRL_RST_SGDMA) |
119 BIT(OX820_SYS_CTRL_RST_CIPHER) |
120 BIT(OX820_SYS_CTRL_RST_SATA) |
121 BIT(OX820_SYS_CTRL_RST_SATA_LINK) |
122 BIT(OX820_SYS_CTRL_RST_SATA_PHY) |
123 BIT(OX820_SYS_CTRL_RST_PCIEPHY) |
124 BIT(OX820_SYS_CTRL_RST_STATIC) |
125 BIT(OX820_SYS_CTRL_RST_UART1) |
126 BIT(OX820_SYS_CTRL_RST_UART2) |
127 BIT(OX820_SYS_CTRL_RST_MISC) |
128 BIT(OX820_SYS_CTRL_RST_I2S) |
129 BIT(OX820_SYS_CTRL_RST_SD) |
130 BIT(OX820_SYS_CTRL_RST_MACB) |
131 BIT(OX820_SYS_CTRL_RST_PCIEB) |
132 BIT(OX820_SYS_CTRL_RST_VIDEO) |
133 BIT(OX820_SYS_CTRL_RST_USBHSPHYB) |
134 BIT(OX820_SYS_CTRL_RST_USBDEV);
135
136 regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
137
138 /* Release reset to cores as per power on defaults */
139 regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET,
140 BIT(OX820_SYS_CTRL_RST_GPIO));
141
142 /*
143 * Disable clocks to cores as per power-on defaults - must leave DDR
144 * related clocks enabled otherwise we'll stop rather abruptly.
145 */
146 value = BIT(OX820_SYS_CTRL_CLK_COPRO) |
147 BIT(OX820_SYS_CTRL_CLK_DMA) |
148 BIT(OX820_SYS_CTRL_CLK_CIPHER) |
149 BIT(OX820_SYS_CTRL_CLK_SD) |
150 BIT(OX820_SYS_CTRL_CLK_SATA) |
151 BIT(OX820_SYS_CTRL_CLK_I2S) |
152 BIT(OX820_SYS_CTRL_CLK_USBHS) |
153 BIT(OX820_SYS_CTRL_CLK_MAC) |
154 BIT(OX820_SYS_CTRL_CLK_PCIEA) |
155 BIT(OX820_SYS_CTRL_CLK_STATIC) |
156 BIT(OX820_SYS_CTRL_CLK_MACB) |
157 BIT(OX820_SYS_CTRL_CLK_PCIEB) |
158 BIT(OX820_SYS_CTRL_CLK_REF600) |
159 BIT(OX820_SYS_CTRL_CLK_USBDEV);
160
161 regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);
162
163 /* Enable clocks to cores as per power-on defaults */
164
165 /* Set sys-control pin mux'ing as per power-on defaults */
166 regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);
167 regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);
168 regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);
169 regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);
170 regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);
171 regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);
172
173 regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);
174 regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);
175 regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);
176 regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);
177 regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
178 regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);
179
180 /*
181 * No need to save any state, as the ROM loader can determine whether
182 * reset is due to power cycling or programatic action, just hit the
183 * (self-clearing) CPU reset bit of the block reset register
184 */
185 value =
186 BIT(OX820_SYS_CTRL_RST_SCU) |
187 BIT(OX820_SYS_CTRL_RST_ARM0) |
188 BIT(OX820_SYS_CTRL_RST_ARM1);
189
190 regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
191
192 pr_emerg("Unable to restart system\n");
193 return NOTIFY_DONE;
194 }
195
ox820_restart_probe(struct platform_device * pdev)196 static int ox820_restart_probe(struct platform_device *pdev)
197 {
198 struct oxnas_restart_context *ctx;
199 struct regmap *sys_ctrl;
200 struct device *dev = &pdev->dev;
201 int err = 0;
202
203 sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);
204 if (IS_ERR(sys_ctrl))
205 return PTR_ERR(sys_ctrl);
206
207 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
208 if (!ctx)
209 return -ENOMEM;
210
211 ctx->sys_ctrl = sys_ctrl;
212 ctx->restart_handler.notifier_call = ox820_restart_handle;
213 ctx->restart_handler.priority = 192;
214 err = register_restart_handler(&ctx->restart_handler);
215 if (err)
216 dev_err(dev, "can't register restart notifier (err=%d)\n", err);
217
218 return err;
219 }
220
221 static const struct of_device_id ox820_restart_of_match[] = {
222 { .compatible = "oxsemi,ox820-sys-ctrl" },
223 {}
224 };
225
226 static struct platform_driver ox820_restart_driver = {
227 .probe = ox820_restart_probe,
228 .driver = {
229 .name = "ox820-chip-reset",
230 .of_match_table = ox820_restart_of_match,
231 },
232 };
233 builtin_platform_driver(ox820_restart_driver);
234