Searched refs:OSC (Results 1 – 11 of 11) sorted by relevance
| /linux-5.19.10/drivers/clk/loongson1/ |
| D | clk-loongson1c.c | 13 #define OSC (24 * 1000000) macro
25 rate *= OSC; in ls1x_pll_recalc_rate()
47 hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); in ls1x_clk_init()
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| D | clk-loongson1b.c | 14 #define OSC (33 * 1000000) macro
26 rate *= OSC; in ls1x_pll_recalc_rate()
44 hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); in ls1x_clk_init()
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| /linux-5.19.10/drivers/clk/versatile/ |
| D | Kconfig | 23 tristate "Clock driver for Versatile Express OSC clock generators"
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | imx6ulz-bsh-smm-m2.dts | 143 MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */
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| D | sun8i-a83t.dtsi | 176 * This is called "internal OSC" in some places.
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| /linux-5.19.10/arch/alpha/kernel/ |
| D | smc37c93x.c | 54 #define OSC 0x24 macro
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| /linux-5.19.10/Documentation/devicetree/bindings/clock/ |
| D | tesla,fsd-clock.yaml | 16 The root clock comes from external OSC clock (24 MHz).
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| /linux-5.19.10/Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,exynos-hdmi.yaml | 86 VDD 1.8V HDMI OSC.
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| /linux-5.19.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-host.txt | 57 using 24MHz OSC for RC's PHY.
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| /linux-5.19.10/drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 202 LPC32XX_CLK_DEFINE(OSC, "osc", CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL),
1226 LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
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| /linux-5.19.10/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra20.c | 2054 MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
2055 MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
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