Searched refs:NUM_UCLK_DPM_LEVELS (Results 1 – 15 of 15) sorted by relevance
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/ |
D | smu9_driver_if.h | 41 #define NUM_UCLK_DPM_LEVELS 4 macro 50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 220 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */ 221 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */ 222 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
|
D | smu11_driver_if.h | 42 #define NUM_UCLK_DPM_LEVELS 4 macro 57 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 424 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
D | smu13_driver_if_v13_0_0.h | 44 #define NUM_UCLK_DPM_LEVELS 4 macro 1009 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1069 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1070 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:… 1072 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1073 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1329 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1481 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1482 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1483 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS];
|
D | smu13_driver_if_v13_0_7.h | 43 #define NUM_UCLK_DPM_LEVELS 4 macro 1031 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1091 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1092 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:… 1094 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1095 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1352 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1501 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1502 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1503 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS];
|
D | smu11_driver_if_sienna_cichlid.h | 45 #define NUM_UCLK_DPM_LEVELS 4 macro 64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 684 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 697 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, … 706 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 707 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 746 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1043 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1056 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, … 1065 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) [all …]
|
D | smu13_driver_if_aldebaran.h | 31 #define NUM_UCLK_DPM_LEVELS 4 macro 301 uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK 302 uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
|
D | smu11_driver_if_navi10.h | 45 #define NUM_UCLK_DPM_LEVELS 4 macro 60 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 588 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 598 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, … 603 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 604 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
|
D | smu11_driver_if_arcturus.h | 39 #define NUM_UCLK_DPM_LEVELS 4 macro 49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 518 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/ |
D | smu9_driver_if.h | 40 #define NUM_UCLK_DPM_LEVELS 4 macro 53 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 312 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
D | sienna_cichlid_ppt.c | 2666 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2684 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2699 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2703 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 2749 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable() 3304 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3322 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3337 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3341 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable() 3387 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
|
D | arcturus_ppt.c | 1786 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
D | vega20_processpptables.c | 333 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
|
D | vega10_hwmgr.c | 1891 while (i < NUM_UCLK_DPM_LEVELS) { in vega10_populate_all_memory_levels() 3589 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; in vega10_get_soc_index_for_max_uclk() 3615 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) in vega10_upload_dpm_bootup_level()
|
D | vega12_hwmgr.c | 2497 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega12_set_uclk_to_highest_dpm_level()
|
D | vega20_hwmgr.c | 3581 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega20_set_uclk_to_highest_dpm_level()
|