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Searched refs:NUM_FCLK_DPM_LEVELS (Results 1 – 16 of 16) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu10_driver_if.h102 #define NUM_FCLK_DPM_LEVELS 4 macro
113 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
Dsmu11_driver_if.h43 #define NUM_FCLK_DPM_LEVELS 8 macro
58 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
425 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu12_driver_if.h107 #define NUM_FCLK_DPM_LEVELS 4 macro
119 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
Dsmu11_driver_if_vangogh.h110 #define NUM_FCLK_DPM_LEVELS 4 macro
138 df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
Dsmu13_driver_if_aldebaran.h32 #define NUM_FCLK_DPM_LEVELS 8 macro
299 uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
300 uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
Dsmu13_driver_if_v13_0_0.h46 #define NUM_FCLK_DPM_LEVELS 8 macro
1015 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1077 …uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM s…
1078 …uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK …
1079 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1335 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
Dsmu13_driver_if_v13_0_7.h45 #define NUM_FCLK_DPM_LEVELS 8 macro
1037 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1099 …uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM s…
1100 …uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK …
1101 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1358 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
Dsmu11_driver_if_arcturus.h40 #define NUM_FCLK_DPM_LEVELS 8 macro
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
519 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
Dsmu11_driver_if_sienna_cichlid.h48 #define NUM_FCLK_DPM_LEVELS 8 macro
67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
690 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1049 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c209 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
219 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
563 count = NUM_FCLK_DPM_LEVELS; in renoir_print_clk_levels()
764 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in renoir_get_dpm_clock_table()
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c1951 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in vangogh_get_dpm_clock_table()
1956 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in vangogh_get_dpm_clock_table()
Darcturus_ppt.c1790 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
Dsienna_cichlid_ppt.c2670 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
3308 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_processpptables.c337 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
Dsmu10_hwmgr.c503 NUM_FCLK_DPM_LEVELS, in smu10_populate_clock_table()
Dvega20_hwmgr.c3607 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS, in vega20_set_fclk_to_highest_dpm_level()