Searched refs:NPCM7XX_REG_TISR (Results 1 – 1 of 1) sorted by relevance
27 #define NPCM7XX_REG_TISR 0x18 /* Timer Interrupt Status Register */ macro127 writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR); in npcm7xx_timer0_interrupt()161 timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR); in npcm7xx_clockevents_init()