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Searched refs:MinVddcPhases (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/radeon/
Dsmu7_discrete.h107 uint32_t MinVddcPhases; member
138 uint32_t MinVddcPhases; member
171 uint32_t MinVddcPhases; member
245 uint8_t MinVddcPhases; member
Dci_dpm.c2628 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2870 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()
2876 &memory_level->MinVddcPhases); in ci_populate_single_memory_level()
2933 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); in ci_populate_single_memory_level()
2971 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3001 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()
3013 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
3199 graphic_level->MinVddcPhases = 1; in ci_populate_single_graphic_level()
3205 &graphic_level->MinVddcPhases); in ci_populate_single_graphic_level()
3226 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); in ci_populate_single_graphic_level()
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/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu7_discrete.h107 uint32_t MinVddcPhases; member
138 uint32_t MinVddcPhases; member
171 uint32_t MinVddcPhases; member
245 uint8_t MinVddcPhases; member
Dsmu71_discrete.h50 uint32_t MinVddcPhases; member
80 uint32_t MinVddcPhases; member
113 uint32_t MinVddcPhases; member
191 uint8_t MinVddcPhases; member
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c909 graphic_level->MinVddcPhases = 1; in iceland_populate_single_graphic_level()
915 &graphic_level->MinVddcPhases); in iceland_populate_single_graphic_level()
945 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases); in iceland_populate_single_graphic_level()
1258 memory_level->MinVddcPhases = 1; in iceland_populate_single_memory_level()
1262 memory_clock, &memory_level->MinVddcPhases); in iceland_populate_single_memory_level()
1325 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); in iceland_populate_single_memory_level()
1445 table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1; in iceland_populate_smc_acpi_level()
1493 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in iceland_populate_smc_acpi_level()
Dci_smumgr.c428 level->MinVddcPhases = 1; in ci_populate_single_graphic_level()
434 &level->MinVddcPhases); in ci_populate_single_graphic_level()
459 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases); in ci_populate_single_graphic_level()
1213 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()
1217 memory_clock, &memory_level->MinVddcPhases); in ci_populate_single_memory_level()
1280 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); in ci_populate_single_memory_level()
1400 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
1448 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
1537 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()