Searched refs:MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK (Results 1 – 2 of 2) sorted by relevance
87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; in mv88e6xxx_port_set_rgmii_delay()98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", in mv88e6xxx_port_set_rgmii_delay()
73 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 macro