| /linux-5.19.10/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7724.c | 28 #define MSTPCR2 0xa4150038 macro
234 [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
235 [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
236 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),
237 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
238 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
239 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
240 [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),
241 [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),
242 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),
[all …]
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| D | clock-sh7723.c | 27 #define MSTPCR2 0xa4150038 macro
173 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
174 [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
175 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
176 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
177 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
178 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
179 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
180 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
[all …]
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| D | clock-sh7343.c | 23 #define MSTPCR2 0xa4150038 macro
166 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
167 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
168 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
169 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
170 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
171 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
172 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
173 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
174 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
[all …]
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| D | clock-sh7366.c | 23 #define MSTPCR2 0xa4150038 macro
166 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
167 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
168 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
169 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
170 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
171 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
172 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
173 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
174 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
[all …]
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| D | clock-sh7722.c | 26 #define MSTPCR2 0xa4150038 macro
155 [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
156 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
157 [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
158 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
159 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
160 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
161 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
162 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
163 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
[all …]
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| D | clock-sh7757.c | 77 #define MSTPCR2 0xffc10028 macro
99 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
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| /linux-5.19.10/arch/sh/boot/romimage/ |
| D | mmcif-sh7724.c | 16 #define MSTPCR2 0xa4150038 macro
42 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader()
75 __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); in mmcif_loader()
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| /linux-5.19.10/arch/sh/include/cpu-sh4/cpu/ |
| D | freq.h | 21 #define MSTPCR2 0xa4150038 macro
45 #define MSTPCR2 0xa4150038 macro
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