Searched refs:MIPI (Results 1 – 25 of 197) sorted by relevance
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/linux-5.19.10/Documentation/devicetree/bindings/display/bridge/ |
D | toshiba,tc358762.yaml | 7 title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge 13 The TC358762 is bridge device which converts MIPI DSI to MIPI DPI. 34 Video port for MIPI DSI input 39 Video port for MIPI DPI output (panel or connector).
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D | lontium,lt9211.yaml | 41 Primary MIPI DSI port-1 for MIPI input or 47 Additional MIPI port-2 for MIPI input or LVDS port-2 54 Primary MIPI DSI port-1 for MIPI output or 60 Additional MIPI port-2 for MIPI output or LVDS port-2
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D | lontium,lt9611.yaml | 7 title: Lontium LT9611(UXC) 2 Port MIPI to HDMI Bridge 35 description: Regulator for 1.8V MIPI phy power. 47 Primary MIPI port-1 for MIPI input 52 Additional MIPI port-2 for MIPI input, used in combination 53 with primary MIPI port-1 to drive higher resolution displays
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D | chipone,icn6211.yaml | 7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge 13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone. 15 It has a flexible configuration of MIPI DSI signal input and 31 description: A 1.8V/2.5V/3.3V supply that power the MIPI RX. 47 Video port for MIPI DSI input 67 Video port for MIPI DPI output (panel or connector).
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D | intel,keembay-dsi.yaml | 19 - description: MIPI registers range 27 - description: MIPI DSI clock 28 - description: MIPI DSI econfig clock 29 - description: MIPI DSI config clock 43 description: MIPI DSI input port.
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/linux-5.19.10/drivers/media/platform/cadence/ |
D | Kconfig | 6 tristate "Cadence MIPI-CSI2 RX Controller" 12 Support for the Cadence MIPI CSI2 Receiver controller. 18 tristate "Cadence MIPI-CSI2 TX Controller" 24 Support for the Cadence MIPI CSI2 Transceiver controller.
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/linux-5.19.10/Documentation/devicetree/bindings/media/xilinx/ |
D | xlnx,csi2rxss.yaml | 7 title: Xilinx MIPI CSI-2 Receiver Subsystem 13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 16 The subsystem consists of a MIPI D-PHY in slave mode which captures the 17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the 20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem. 21 Please note that this bindings includes only the MIPI CSI-2 Rx controller 118 connects to MIPI CSI-2 source like sensor. 196 /* MIPI CSI-2 Camera handle */
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/linux-5.19.10/Documentation/devicetree/bindings/media/i2c/ |
D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge 3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts 4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C. 20 MIPI CSI-2 clock is continuous or non-continuous. 25 For further information on the MIPI CSI-2 endpoint node properties, see
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D | isil,isl79987.yaml | 7 title: Intersil ISL79987 Analog to MIPI CSI-2 decoder 14 The Intersil ISL79987 is an analog to MIPI CSI-2 decoder which is capable of 15 receiving up to four analog stream and multiplexing them into up to four MIPI 16 CSI-2 virtual channels, using one MIPI clock lane and 1/2 data lanes.
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/linux-5.19.10/Documentation/devicetree/bindings/phy/ |
D | rockchip-mipi-dphy-rx0.yaml | 7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings 14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to 23 - description: MIPI D-PHY ref clock 24 - description: MIPI D-PHY RX0 cfg clock 53 * MIPI D-PHY RX0 use registers in "general register files", it
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D | samsung,mipi-video-phy.yaml | 7 title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY 17 0 - MIPI CSIS 0, 18 1 - MIPI DSIM 0, 19 2 - MIPI CSIS 1, 20 3 - MIPI DSIM 1. 24 4 - MIPI CSIS 2.
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D | allwinner,sun6i-a31-mipi-dphy.yaml | 7 title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings 44 - "rx" for receiving (e.g. when used with MIPI CSI-2); 45 - "tx" for transmitting (e.g. when used with MIPI DSI).
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/linux-5.19.10/Documentation/devicetree/bindings/media/ |
D | samsung-mipi-csis.txt | 1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS) 11 - interrupts : should contain MIPI CSIS interrupt; the format of the 14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V); 15 - vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V); 42 - data-lanes : (required) an array specifying active physical MIPI-CSI2
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D | imx.txt | 27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX 28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core 39 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx 46 connecting with a MIPI CSI-2 source, and ports 1 49 MIPI CSI-2 virtual channel outputs.
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D | nxp,imx-mipi-csi2.yaml | 7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver 14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is 40 - description: The MIPI D-PHY clock 55 description: The MIPI D-PHY digital power supply 59 - description: MIPI D-PHY slave reset
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/linux-5.19.10/Documentation/devicetree/bindings/i3c/ |
D | mipi-i3c-hci.yaml | 7 title: MIPI I3C HCI Device Tree Bindings 16 MIPI I3C Host Controller Interface 18 The MIPI I3C HCI (Host Controller Interface) specification defines 19 a common software driver interface to support compliant MIPI I3C
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/linux-5.19.10/drivers/phy/rockchip/ |
D | Kconfig | 13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver" 18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0 52 tristate "Rockchip Innosilicon MIPI CSI PHY driver" 57 Enable this to support the Rockchip MIPI CSI PHY with 61 tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver" 66 Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
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/linux-5.19.10/Documentation/driver-api/soundwire/ |
D | summary.rst | 5 SoundWire is a new interface ratified in 2015 by the MIPI Alliance. 58 The MIPI SoundWire specification uses the term 'device' to refer to a Master 69 Programs all the MIPI-defined Slave registers. Represents a SoundWire 77 Driver controlling the Slave device. MIPI-specified registers are controlled 91 Bus implements API to read standard Master MIPI properties and also provides 133 MIPI specification, so Bus calls the "sdw_master_port_ops" callback 141 The MIPI specification requires each Slave interface to expose a unique 154 board-file, ACPI or DT. The MIPI Software specification defines additional 181 For capabilities, Bus implements API to read standard Slave MIPI properties 198 SoundWire MIPI specification 1.1 is available at: [all …]
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/linux-5.19.10/Documentation/devicetree/bindings/soundwire/ |
D | qcom,sdw.txt | 71 More info in MIPI Alliance SoundWire 1.0 Specifications. 80 More info in MIPI Alliance SoundWire 1.0 Specifications. 90 More info in MIPI Alliance SoundWire 1.0 Specifications. 98 More info in MIPI Alliance SoundWire 1.0 Specifications. 109 More info in MIPI Alliance SoundWire 1.0 Specifications. 119 More info in MIPI Alliance SoundWire 1.0 Specifications. 129 More info in MIPI Alliance SoundWire 1.0 Specifications. 140 More info in MIPI Alliance SoundWire 1.0 Specifications. 151 More info in MIPI Alliance SoundWire 1.0 Specifications. 163 More info in MIPI Alliance SoundWire 1.0 Specifications. [all …]
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/linux-5.19.10/drivers/hwtracing/stm/ |
D | Kconfig | 8 Trace Protocol (STP) format as defined by MIPI STP standards. 21 exclusively until the MIPI SyS-T support was added. Use this 24 The receiving side only needs to be able to decode the MIPI 31 tristate "MIPI SyS-T STM framing protocol driver" 34 This is an implementation of MIPI SyS-T protocol to be used 40 addition to the MIPI STP, in order to extract the data.
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/linux-5.19.10/drivers/phy/amlogic/ |
D | Kconfig | 69 Enable this to support the Meson MIPI + PCIE PHY found 74 tristate "Meson AXG MIPI + PCIE analog PHY driver" 81 Enable this to support the Meson MIPI + PCIE analog PHY 86 tristate "Meson AXG MIPI DPHY driver" 93 Enable this to support the Meson MIPI DPHY found in Meson AXG
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/linux-5.19.10/Documentation/trace/ |
D | sys-t.rst | 4 MIPI SyS-T over STP 7 The MIPI SyS-T protocol driver can be used with STM class devices to 11 In order to use the MIPI SyS-T protocol driver with your STM device, 33 Now, with the MIPI SyS-T protocol driver, each policy node in the 52 MIPI SyS-T message header. It is off by default as the STP already
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/linux-5.19.10/Documentation/devicetree/bindings/display/exynos/ |
D | exynos_dsim.txt | 1 Exynos MIPI DSI Master 19 - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) 20 - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) 23 according to DSI host bindings (see MIPI DSI bindings [1]) 32 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
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/linux-5.19.10/Documentation/admin-guide/media/ |
D | imx7.rst | 16 - MIPI CSI-2 Receiver 20 MIPI Camera Input ---> MIPI CSI-2 --- > |\ 39 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel 40 data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the 48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has 55 can interface directly with Parallel and MIPI CSI-2 buses. It has 256 x 64 FIFO 76 On this platform an OV2680 MIPI CSI-2 module is connected to the internal MIPI
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/linux-5.19.10/Documentation/devicetree/bindings/display/panel/ |
D | sitronix,st7701.yaml | 15 several system interfaces like MIPI/RGB/SPI. 17 Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has 35 description: analog regulator for MIPI circuit
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