Searched refs:MDIO_WC_REG_RX0_PCI_CTRL (Results 1 – 2 of 2) sorted by relevance
7390 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba macro
3856 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); in bnx2x_warpcore_enable_AN_KR()3871 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), in bnx2x_warpcore_enable_AN_KR()