Searched refs:MCDE_CRX1_CLKSEL_CLKPLL72 (Results 1 – 2 of 2) sorted by relevance
29 val |= MCDE_CRX1_CLKSEL_CLKPLL72 << MCDE_CRX1_CLKSEL_SHIFT; in mcde_clk_div_enable()
440 #define MCDE_CRX1_CLKSEL_CLKPLL72 0 macro