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Searched refs:LVL_1_INST (Results 1 – 1 of 1) sorted by relevance

/linux-5.19.10/arch/x86/kernel/cpu/
Dcacheinfo.c26 #define LVL_1_INST 1 macro
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
58 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
813 case LVL_1_INST: in init_intel_cacheinfo()