Searched refs:LEVEL0_MPLL_DIV_EN (Results 1 – 2 of 2) sorted by relevance
85 # define LEVEL0_MPLL_DIV_EN (1 << 28) macro
374 LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN); in rv6xx_memory_clock_entry_enable_post_divider()376 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); in rv6xx_memory_clock_entry_enable_post_divider()