Searched refs:Interrupt (Results 1 – 25 of 418) sorted by relevance
12345678910>>...17
| /linux-5.19.10/Documentation/devicetree/bindings/i2c/ |
| D | renesas,riic.yaml | 32 - description: Transmit End Interrupt
33 - description: Receive Data Full Interrupt
34 - description: Transmit Data Empty Interrupt
35 - description: Stop Condition Detection Interrupt
36 - description: Start Condition Detection Interrupt
37 - description: NACK Reception Interrupt
38 - description: Arbitration-Lost Interrupt
39 - description: Timeout Interrupt
|
| /linux-5.19.10/drivers/irqchip/ |
| D | Kconfig | 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
227 Enable support for the Renesas Interrupt Controller for external
235 Enable support for the Renesas Interrupt Controller for external
242 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
250 Interrupt controller driver for the board management controller
300 bool "Xilinx Interrupt Controller IP"
304 Support for the Xilinx Interrupt Controller IP core.
408 Support for the UniPhier AIDET (ARM Interrupt Detector).
411 tristate "Meson GPIO Interrupt Multiplexer"
[all …]
|
| /linux-5.19.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | renesas,intc-irqpin.yaml | 7 title: Renesas Interrupt Controller (INTC) for external pins
25 - description: Interrupt control register
26 - description: Interrupt priority register
27 - description: Interrupt source register
28 - description: Interrupt mask register
29 - description: Interrupt mask clear register
30 - description: Interrupt control register for ICR0 with IRLM0 bit
|
| D | csky,mpintc.txt | 2 C-SKY Multi-processors Interrupt Controller
5 C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
8 Interrupt number definition:
13 Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
|
| D | ti,sci-intr.yaml | 7 title: Texas Instruments K3 Interrupt Router
16 The Interrupt Router (INTR) module provides a mechanism to mux M
18 to be driven per N output. An Interrupt Router can either handle edge
21 Interrupt Router
71 Interrupt ranges that converts the INTR output hw irq numbers
|
| D | img,pdc-intc.txt | 1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
30 * Interrupt Specifier Definition
32 Interrupt specifiers consists of 2 cells encoded as follows:
88 // Interrupt source Peripheral 0
102 // Interrupt source SysWake 0 that is active-low level-sensitive
|
| D | kontron,sl28cpld-intc.yaml | 7 title: Interrupt controller driver for the sl28cpld board management controller
22 0 RTC_INT# Interrupt line from on-board RTC
28 6 watchdog Interrupt of the internal watchdog
|
| D | cdns,xtensa-mx.txt | 1 * Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX)
|
| D | ti,sci-inta.yaml | 7 title: Texas Instruments K3 Interrupt Aggregator
16 The Interrupt Aggregator (INTA) provides a centralized machine
21 Interrupt Aggregator
67 Interrupt ranges that converts the INTA output hw irq numbers
|
| D | intel,ce4100-ioapic.txt | 1 Interrupt chips
4 * Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
|
| D | fsl,ls-extirq.yaml | 7 title: Freescale Layerscape External Interrupt Controller
46 Specifies the Interrupt Polarity Control Register (INTPCR) in the
47 SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
|
| D | ti,cp-intc.txt | 1 * TI Common Platform Interrupt Controller
3 Common Platform Interrupt Controller (cp_intc) is used on
|
| D | amazon,al-fic.txt | 1 Amazon's Annapurna Labs Fabric Interrupt Controller
16 Interrupt Controllers bindings used by client devices.
|
| D | marvell,sei.txt | 1 Marvell SEI (System Error Interrupt) Controller
4 Marvell SEI (System Error Interrupt) controller is an interrupt
|
| /linux-5.19.10/Documentation/loongarch/ |
| D | irq-chip-model.rst | 9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
157 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
|
| /linux-5.19.10/Documentation/devicetree/bindings/usb/ |
| D | lpc32xx-udc.txt | 8 * USB Device Low Priority Interrupt
9 * USB Device High Priority Interrupt
10 * USB Device DMA Interrupt
11 * External USB Transceiver Interrupt (OTG ATX)
|
| /linux-5.19.10/Documentation/translations/zh_CN/loongarch/ |
| D | irq-chip-model.rst | 13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
62 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
|
| /linux-5.19.10/Documentation/devicetree/bindings/timer/ |
| D | allwinner,sun5i-a13-hstimer.yaml | 28 - description: Timer 0 Interrupt
29 - description: Timer 1 Interrupt
30 - description: Timer 2 Interrupt
31 - description: Timer 3 Interrupt
|
| D | samsung,exynos4210-mct.yaml | 53 0: Global Timer Interrupt 0
54 1: Global Timer Interrupt 1
55 2: Global Timer Interrupt 2
56 3: Global Timer Interrupt 3
57 4: Local Timer Interrupt 0
58 5: Local Timer Interrupt 1
61 i: Local Timer Interrupt n
|
| D | snps,arc-timer.txt | 1 Synopsys ARC Local Timer with Interrupt Capabilities
11 - interrupts : single Interrupt going into parent intc
|
| /linux-5.19.10/Documentation/scsi/ |
| D | hptiop.rst | 28 0x24 Inbound Interrupt Status Register
29 0x28 Inbound Interrupt Mask Register
30 0x30 Outbound Interrupt Status Register
31 0x34 Outbound Interrupt Mask Register
46 0x24 Inbound Interrupt Status Register
47 0x28 Inbound Interrupt Mask Register
48 0x30 Outbound Interrupt Status Register
49 0x34 Outbound Interrupt Mask Register
60 0x20404 Inbound Interrupt Mask Register
62 0x2040C Outbound Interrupt Mask Register
[all …]
|
| /linux-5.19.10/Documentation/devicetree/bindings/net/ |
| D | davinci_emac.txt | 15 4 sources: <Receive Threshold Interrupt
16 Receive Interrupt
17 Transmit Interrupt
18 Miscellaneous Interrupt>
|
| /linux-5.19.10/Documentation/devicetree/bindings/crypto/ |
| D | hisilicon,hip07-sec.txt | 13 - interrupts: Interrupt specifiers.
16 Interrupt 0 is for the SEC unit error queue.
17 Interrupt 2N + 1 is the completion interrupt for queue N.
18 Interrupt 2N + 2 is the error interrupt for queue N.
|
| D | amlogic,gxl-crypto.yaml | 22 - description: "Interrupt for flow 0"
23 - description: "Interrupt for flow 1"
|
| /linux-5.19.10/Documentation/virt/kvm/devices/ |
| D | xive.rst | 4 POWER9 eXternal Interrupt Virtualization Engine (XIVE Gen1)
8 - KVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1
25 1. Thread Interrupt Management Area (TIMA)
27 Each thread has an associated Thread Interrupt Management context
32 - Interrupt Pending Buffer (IPB)
103 Interrupt source number (64-bit)
116 -E2BIG Interrupt source number is out of range
126 Interrupt source number (64-bit)
136 - eisn: Effective Interrupt Source Number
199 Interrupt source number (64-bit)
|
12345678910>>...17