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Searched refs:IS_CHERRYVIEW (Results 1 – 25 of 52) sorted by relevance

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/linux-5.19.10/drivers/gpu/drm/i915/display/
Dg4x_dp.c51 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; in vlv_get_dpll()
67 } else if (IS_CHERRYVIEW(dev_priv)) { in g4x_dp_set_clock()
161 if (IS_CHERRYVIEW(dev_priv)) in intel_dp_prepare()
290 else if (IS_CHERRYVIEW(dev_priv)) in g4x_dp_port_enabled()
482 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
667 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
677 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
680 if (IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
1279 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1329 if (IS_CHERRYVIEW(dev_priv)) { in g4x_dp_init()
[all …]
Dintel_pipe_crc.c154 if (!IS_CHERRYVIEW(dev_priv)) in vlv_pipe_crc_ctl_reg()
417 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
547 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
623 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
Dintel_pps.c78 if (IS_CHERRYVIEW(dev_priv)) in vlv_power_sequencer_kick()
90 release_cl_override = IS_CHERRYVIEW(dev_priv) && in vlv_power_sequencer_kick()
369 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
411 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
424 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1304 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1365 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
1395 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_unlock_regs_wa()
1412 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_setup()
1451 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in assert_pps_unlocked()
Di9xx_plane.c138 if (IS_CHERRYVIEW(dev_priv)) in i9xx_plane_has_windowing()
462 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { in i9xx_plane_update_arm()
803 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
837 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
868 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
910 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1014 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
Dintel_lpe_audio.c120 pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */ in lpe_audio_platdev_create()
185 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
Dg4x_hdmi.c52 else if (IS_CHERRYVIEW(dev_priv)) in intel_hdmi_prepare()
555 if (IS_CHERRYVIEW(dev_priv)) { in g4x_hdmi_init()
580 if (IS_CHERRYVIEW(dev_priv)) { in g4x_hdmi_init()
Dintel_vga.c18 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
Dintel_cdclk.c546 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
553 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
2202 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
2270 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2809 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
2878 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
2912 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3043 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3223 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
Dintel_sprite.c462 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_sprite_update_arm()
1406 if (IS_CHERRYVIEW(dev_priv) && in chv_plane_check_rotation()
1502 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_sprite_set_colorkey_ioctl()
1741 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_sprite_plane_create()
1750 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1800 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
Dvlv_dsi_pll.c75 if (IS_CHERRYVIEW(dev_priv)) { in dsi_calc_mnp()
270 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; in vlv_dsi_get_pclk()
Dintel_dsi_vbt.c402 else if (IS_CHERRYVIEW(dev_priv)) in mipi_exec_gpio()
882 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_init()
942 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_cleanup()
Dintel_drrs.c72 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_drrs_set_refresh_rate_pipeconf()
Dintel_crtc.c340 if (IS_CHERRYVIEW(dev_priv) || in intel_crtc_init()
486 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_pipe_update_start()
Dintel_display.c276 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
2275 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
2286 if (IS_CHERRYVIEW(dev_priv)) in valleyview_crtc_enable()
2395 if (IS_CHERRYVIEW(dev_priv)) in i9xx_crtc_disable()
2938 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); in intel_cpu_transcoder_has_m2_n2()
3153 IS_CHERRYVIEW(dev_priv)) { in i9xx_set_pipeconf()
3185 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_set_pipeconf()
3358 IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
3375 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
3383 if (IS_CHERRYVIEW(dev_priv)) in i9xx_get_pipe_config()
[all …]
/linux-5.19.10/drivers/gpu/drm/i915/gt/
Dintel_gtt.c29 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); in intel_vm_no_concurrent_access_wa()
427 else if (IS_CHERRYVIEW(i915)) in gtt_write_workarounds()
595 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) in setup_private_pat()
Dintel_rc6.c565 if (IS_CHERRYVIEW(i915)) in intel_rc6_init()
603 if (IS_CHERRYVIEW(i915)) in intel_rc6_enable()
770 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
Dintel_rps.c838 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1497 else if (IS_CHERRYVIEW(i915)) in intel_rps_enable()
1592 else if (IS_CHERRYVIEW(i915)) in intel_gpu_freq()
1609 else if (IS_CHERRYVIEW(i915)) in intel_freq_opcode()
1825 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; in rps_work()
1841 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; in rps_work()
1968 if (IS_CHERRYVIEW(i915)) in intel_rps_init()
2035 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
2056 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in read_cagf()
Dselftest_rc6.c51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
Dintel_gt_sysfs_pm.c254 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in intel_sysfs_rc6_init()
573 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in intel_sysfs_rps_init()
Dintel_gt_pm_debugfs.c276 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
307 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_gt_pm_frequency_dump()
Dintel_sseu_debugfs.c271 if (IS_CHERRYVIEW(i915)) in intel_sseu_status()
/linux-5.19.10/drivers/gpu/drm/i915/selftests/
Dintel_uncore.c169 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
281 !IS_CHERRYVIEW(gt->i915)) in live_forcewake_domains()
/linux-5.19.10/drivers/gpu/drm/i915/
Dvlv_suspend.c398 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
443 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
Dvlv_sideband.c221 if (IS_CHERRYVIEW(i915)) in vlv_dpio_phy_iosf_port()
Di915_irq.c192 IS_CHERRYVIEW(dev_priv)) in intel_hpd_init_pins()
1593 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
1632 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
1647 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
3017 if (IS_CHERRYVIEW(dev_priv)) in vlv_display_irq_reset()
3051 if (IS_CHERRYVIEW(dev_priv)) in vlv_display_irq_postinstall()
4413 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
4463 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_handler()
4488 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_reset()
4513 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_postinstall()

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