Searched refs:IRO (Results 1 – 4 of 4) sorted by relevance
15 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \20 IRO[157].m2))22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \23 IRO[158].m2))25 (IRO[163].base + ((funcId) * IRO[163].m1))27 (IRO[153].base + ((funcId) * IRO[153].m1))29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \[all …]
1395 #define IRO (bp->iro_arr) macro
86 (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].base \87 + ((core_tx_stats_id) * IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].m1))89 (IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].size)93 (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].base \94 + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].m1))96 (IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].size)100 (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].base \101 + ((core_rx_queue_id) * IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].m1))103 (IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].size)107 (IRO[IRO_ETH_RX_RATE_LIMIT].base \[all …]
769 #define IRO ((const struct iro *)p_hwfn->cdev->iro_arr) macro