Searched refs:INTEN0 (Results 1 – 2 of 2) sorted by relevance
383 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()397 writel(VAL0 | STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()404 writel(STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()411 writel(VAL0 | STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()448 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); in amd8111e_restart()450 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); in amd8111e_restart()545 writel(INTEN0_CLEAR, mmio + INTEN0); in amd8111e_init_hw_default()784 writel(VAL0|RINTEN0, mmio + INTEN0); in amd8111e_rx_poll()1097 intren0 = readl(mmio + INTEN0); in amd8111e_interrupt()1113 writel(RINTEN0, mmio + INTEN0); in amd8111e_interrupt()[all …]
45 #define INTEN0 0x40 /* Interrupt0 enable register*/ macro