Searched refs:IMX8ULP_CLK_XBAR_DIVBUS (Results 1 – 3 of 3) sorted by relevance
195 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;208 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;241 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;256 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;283 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;296 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;328 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,343 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,358 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
35 #define IMX8ULP_CLK_XBAR_DIVBUS 28 macro
203 …clks[IMX8ULP_CLK_XBAR_DIVBUS] = imx_clk_hw_divider_flags("xbar_divbus", "nic_ad_divplat", base + 0… in imx8ulp_clk_cgc1_init()