Searched refs:IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE (Results 1 – 2 of 2) sorted by relevance
80 #define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 macro
270 …clks[IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE] = imx_clk_hw_gate_dis("pll4_pfd0_div1_gate", "pll4_pfd0", ba… in imx8ulp_clk_cgc2_init()