Searched refs:IMX6QDL_CLK_IPU2_DI1_PRE_SEL (Results 1 – 3 of 3) sorted by relevance
47 #define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 macro
402 <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
661 …hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, i… in imx6q_clocks_init()924 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()