Searched refs:IMX6QDL_CLK_IPU1_DI0_PRE_SEL (Results 1 – 4 of 4) sorted by relevance
63 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
399 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
44 #define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 macro
658 …hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, i… in imx6q_clocks_init()921 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()