1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Applied Micro X-Gene SoC Ethernet Classifier structures
3  *
4  * Copyright (c) 2016, Applied Micro Circuits Corporation
5  * Authors: Khuong Dinh <kdinh@apm.com>
6  *          Tanmay Inamdar <tinamdar@apm.com>
7  *          Iyappan Subramanian <isubramanian@apm.com>
8  */
9 
10 #ifndef __XGENE_ENET_CLE_H__
11 #define __XGENE_ENET_CLE_H__
12 
13 #include <linux/io.h>
14 #include <linux/random.h>
15 
16 /* Register offsets */
17 #define INDADDR			0x04
18 #define INDCMD			0x08
19 #define INDCMD_STATUS		0x0c
20 #define DATA_RAM0		0x10
21 #define SNPTR0			0x0100
22 #define SPPTR0			0x0104
23 #define DFCLSRESDBPTR0		0x0108
24 #define DFCLSRESDB00		0x010c
25 #define RSS_CTRL0		0x0000013c
26 
27 #define CLE_CMD_TO		10	/* ms */
28 #define CLE_PKTRAM_SIZE		256	/* bytes */
29 #define CLE_PORT_OFFSET		0x200
30 #define CLE_DRAM_REGS		17
31 
32 #define CLE_DN_TYPE_LEN		2
33 #define CLE_DN_TYPE_POS		0
34 #define CLE_DN_LASTN_LEN	1
35 #define CLE_DN_LASTN_POS	2
36 #define CLE_DN_HLS_LEN		1
37 #define CLE_DN_HLS_POS		3
38 #define CLE_DN_EXT_LEN		2
39 #define	CLE_DN_EXT_POS		4
40 #define CLE_DN_BSTOR_LEN	2
41 #define CLE_DN_BSTOR_POS	6
42 #define CLE_DN_SBSTOR_LEN	2
43 #define CLE_DN_SBSTOR_POS	8
44 #define CLE_DN_RPTR_LEN		12
45 #define CLE_DN_RPTR_POS		12
46 
47 #define CLE_BR_VALID_LEN	1
48 #define CLE_BR_VALID_POS	0
49 #define CLE_BR_NPPTR_LEN	9
50 #define CLE_BR_NPPTR_POS	1
51 #define CLE_BR_JB_LEN		1
52 #define CLE_BR_JB_POS		10
53 #define CLE_BR_JR_LEN		1
54 #define CLE_BR_JR_POS		11
55 #define CLE_BR_OP_LEN		3
56 #define CLE_BR_OP_POS		12
57 #define CLE_BR_NNODE_LEN	9
58 #define CLE_BR_NNODE_POS	15
59 #define CLE_BR_NBR_LEN		5
60 #define CLE_BR_NBR_POS		24
61 
62 #define CLE_BR_DATA_LEN		16
63 #define CLE_BR_DATA_POS		0
64 #define CLE_BR_MASK_LEN		16
65 #define CLE_BR_MASK_POS		16
66 
67 #define CLE_KN_PRIO_POS		0
68 #define CLE_KN_PRIO_LEN		3
69 #define CLE_KN_RPTR_POS		3
70 #define CLE_KN_RPTR_LEN		10
71 #define CLE_TYPE_POS		0
72 #define CLE_TYPE_LEN		2
73 
74 #define CLE_DROP_POS		28
75 #define CLE_DROP_LEN		1
76 #define CLE_DSTQIDL_POS		25
77 #define CLE_DSTQIDL_LEN		7
78 #define CLE_DSTQIDH_POS		0
79 #define CLE_DSTQIDH_LEN		5
80 #define CLE_FPSEL_POS		21
81 #define CLE_FPSEL_LEN		4
82 #define CLE_NFPSEL_POS		17
83 #define CLE_NFPSEL_LEN		4
84 #define CLE_PRIORITY_POS	5
85 #define CLE_PRIORITY_LEN	3
86 
87 #define JMP_ABS			0
88 #define JMP_REL			1
89 #define JMP_FW			0
90 #define JMP_BW			1
91 
92 enum xgene_cle_ptree_nodes {
93 	PKT_TYPE_NODE,
94 	PKT_PROT_NODE,
95 	RSS_IPV4_TCP_NODE,
96 	RSS_IPV4_UDP_NODE,
97 	RSS_IPV4_OTHERS_NODE,
98 	LAST_NODE,
99 	MAX_NODES
100 };
101 
102 enum xgene_cle_byte_store {
103 	NO_BYTE,
104 	FIRST_BYTE,
105 	SECOND_BYTE,
106 	BOTH_BYTES
107 };
108 
109 /* Preclassification operation types */
110 enum xgene_cle_node_type {
111 	INV,
112 	KN,
113 	EWDN,
114 	RES_NODE
115 };
116 
117 /* Preclassification operation types */
118 enum xgene_cle_op_type {
119 	EQT,
120 	NEQT,
121 	LTEQT,
122 	GTEQT,
123 	AND,
124 	NAND
125 };
126 
127 enum xgene_cle_parser {
128 	PARSER0,
129 	PARSER1,
130 	PARSER2,
131 	PARSER_ALL
132 };
133 
134 #define XGENE_CLE_DRAM(type)	(((type) & 0xf) << 28)
135 enum xgene_cle_dram_type {
136 	PKT_RAM,
137 	RSS_IDT,
138 	RSS_IPV4_HASH_SKEY,
139 	PTREE_RAM = 0xc,
140 	AVL_RAM,
141 	DB_RAM
142 };
143 
144 enum xgene_cle_cmd_type {
145 	CLE_CMD_WR = 1,
146 	CLE_CMD_RD = 2,
147 	CLE_CMD_AVL_ADD = 8,
148 	CLE_CMD_AVL_DEL = 16,
149 	CLE_CMD_AVL_SRCH = 32
150 };
151 
152 enum xgene_cle_ipv4_rss_hashtype {
153 	RSS_IPV4_8B,
154 	RSS_IPV4_12B,
155 };
156 
157 enum xgene_cle_prot_type {
158 	XGENE_CLE_TCP,
159 	XGENE_CLE_UDP,
160 	XGENE_CLE_ESP,
161 	XGENE_CLE_OTHER
162 };
163 
164 enum xgene_cle_prot_version {
165 	XGENE_CLE_IPV4,
166 };
167 
168 enum xgene_cle_ptree_dbptrs {
169 	DB_RES_DROP,
170 	DB_RES_DEF,
171 	DB_RES_ACCEPT,
172 	DB_MAX_PTRS
173 };
174 
175 /* RSS sideband signal info */
176 #define SB_IPFRAG_POS	0
177 #define SB_IPFRAG_LEN	1
178 #define SB_IPPROT_POS	1
179 #define SB_IPPROT_LEN	2
180 #define SB_IPVER_POS	3
181 #define SB_IPVER_LEN	1
182 #define SB_HDRLEN_POS	4
183 #define SB_HDRLEN_LEN	12
184 
185 /* RSS indirection table */
186 #define XGENE_CLE_IDT_ENTRIES	128
187 #define IDT_DSTQID_POS		0
188 #define IDT_DSTQID_LEN		12
189 #define IDT_FPSEL_POS		12
190 #define IDT_FPSEL_LEN		5
191 #define IDT_NFPSEL_POS		17
192 #define IDT_NFPSEL_LEN		5
193 #define IDT_FPSEL1_POS		12
194 #define IDT_FPSEL1_LEN		4
195 #define IDT_NFPSEL1_POS		16
196 #define IDT_NFPSEL1_LEN		4
197 
198 struct xgene_cle_ptree_branch {
199 	bool valid;
200 	u16 next_packet_pointer;
201 	bool jump_bw;
202 	bool jump_rel;
203 	u8 operation;
204 	u16 next_node;
205 	u8 next_branch;
206 	u16 data;
207 	u16 mask;
208 };
209 
210 struct xgene_cle_ptree_ewdn {
211 	u8 node_type;
212 	bool last_node;
213 	bool hdr_len_store;
214 	u8 hdr_extn;
215 	u8 byte_store;
216 	u8 search_byte_store;
217 	u16 result_pointer;
218 	u8 num_branches;
219 	struct xgene_cle_ptree_branch branch[6];
220 };
221 
222 struct xgene_cle_ptree_key {
223 	u8 priority;
224 	u16 result_pointer;
225 };
226 
227 struct xgene_cle_ptree_kn {
228 	u8 node_type;
229 	u8 num_keys;
230 	struct xgene_cle_ptree_key key[32];
231 };
232 
233 struct xgene_cle_dbptr {
234 	u8 split_boundary;
235 	u8 mirror_nxtfpsel;
236 	u8 mirror_fpsel;
237 	u16 mirror_dstqid;
238 	u8 drop;
239 	u8 mirror;
240 	u8 hdr_data_split;
241 	u64 hopinfomsbs;
242 	u8 DR;
243 	u8 HR;
244 	u64 hopinfomlsbs;
245 	u16 h0enq_num;
246 	u8 h0fpsel;
247 	u8 nxtfpsel;
248 	u8 fpsel;
249 	u16 dstqid;
250 	u8 cle_priority;
251 	u8 cle_flowgroup;
252 	u8 cle_perflow;
253 	u8 cle_insert_timestamp;
254 	u8 stash;
255 	u8 in;
256 	u8 perprioen;
257 	u8 perflowgroupen;
258 	u8 perflowen;
259 	u8 selhash;
260 	u8 selhdrext;
261 	u8 mirror_nxtfpsel_msb;
262 	u8 mirror_fpsel_msb;
263 	u8 hfpsel_msb;
264 	u8 nxtfpsel_msb;
265 	u8 fpsel_msb;
266 };
267 
268 struct xgene_cle_ptree {
269 	struct xgene_cle_ptree_kn *kn;
270 	struct xgene_cle_dbptr *dbptr;
271 	u32 num_kn;
272 	u32 num_dbptr;
273 	u32 start_node;
274 	u32 start_pkt;
275 	u32 start_dbptr;
276 };
277 
278 struct xgene_enet_cle {
279 	void __iomem *base;
280 	struct xgene_cle_ptree ptree;
281 	enum xgene_cle_parser active_parser;
282 	u32 parsers;
283 	u32 max_nodes;
284 	u32 max_dbptrs;
285 	u32 jump_bytes;
286 };
287 
288 extern const struct xgene_cle_ops xgene_cle3in_ops;
289 
290 #endif /* __XGENE_ENET_CLE_H__ */
291