| /linux-5.19.10/Documentation/devicetree/bindings/media/ |
| D | rockchip-rga.yaml | 75 <&cru HCLK_RGA>,
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| /linux-5.19.10/include/dt-bindings/clock/ |
| D | rk3188-cru-common.h | 126 #define HCLK_RGA 466 macro
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| D | rk3128-cru.h | 137 #define HCLK_RGA 467 macro
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| D | rk3228-cru.h | 136 #define HCLK_RGA 467 macro
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| D | rv1108-cru.h | 154 #define HCLK_RGA 335 macro
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| D | rk3288-cru.h | 188 #define HCLK_RGA 470 macro
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| D | px30-cru.h | 129 #define HCLK_RGA 253 macro
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| D | rk3328-cru.h | 201 #define HCLK_RGA 340 macro
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| D | rk3368-cru.h | 175 #define HCLK_RGA 470 macro
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| D | rk3399-cru.h | 325 #define HCLK_RGA 485 macro
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| D | rk3568-cru.h | 307 #define HCLK_RGA 244 macro
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| /linux-5.19.10/Documentation/devicetree/bindings/power/ |
| D | rockchip,power-controller.yaml | 213 <&cru HCLK_RGA>;
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| /linux-5.19.10/drivers/clk/rockchip/ |
| D | clk-rk3128.c | 474 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
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| D | clk-rk3228.c | 543 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
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| D | clk-rv1108.c | 455 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
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| D | clk-rk3328.c | 718 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
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| D | clk-rk3188.c | 462 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
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| D | clk-rk3368.c | 743 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
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| D | clk-rk3288.c | 784 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
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| D | clk-px30.c | 822 GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
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| D | clk-rk3399.c | 807 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | rk322x.dtsi | 207 <&cru HCLK_RGA>,
698 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
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| D | rk3188.dtsi | 725 <&cru HCLK_RGA>;
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| D | rk3066a.dtsi | 779 <&cru HCLK_RGA>;
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| D | rk3288.dtsi | 780 <&cru HCLK_RGA>,
1012 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
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