1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_MAIN_H
5 #define __HCLGE_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/types.h>
8 #include <linux/phy.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kfifo.h>
11 #include <net/devlink.h>
12
13 #include "hclge_cmd.h"
14 #include "hclge_ptp.h"
15 #include "hnae3.h"
16 #include "hclge_comm_rss.h"
17 #include "hclge_comm_tqp_stats.h"
18
19 #define HCLGE_MOD_VERSION "1.0"
20 #define HCLGE_DRIVER_NAME "hclge"
21
22 #define HCLGE_MAX_PF_NUM 8
23
24 #define HCLGE_VF_VPORT_START_NUM 1
25
26 #define HCLGE_RD_FIRST_STATS_NUM 2
27 #define HCLGE_RD_OTHER_STATS_NUM 4
28
29 #define HCLGE_INVALID_VPORT 0xffff
30
31 #define HCLGE_PF_CFG_BLOCK_SIZE 32
32 #define HCLGE_PF_CFG_DESC_NUM \
33 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
34
35 #define HCLGE_VECTOR_REG_BASE 0x20000
36 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000
37 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
38
39 #define HCLGE_VECTOR_REG_OFFSET 0x4
40 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000
41 #define HCLGE_VECTOR_VF_OFFSET 0x100000
42
43 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
44
45 /* bar registers for common func */
46 #define HCLGE_GRO_EN_REG 0x28000
47 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008
48
49 /* bar registers for rcb */
50 #define HCLGE_RING_RX_ADDR_L_REG 0x80000
51 #define HCLGE_RING_RX_ADDR_H_REG 0x80004
52 #define HCLGE_RING_RX_BD_NUM_REG 0x80008
53 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
54 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014
55 #define HCLGE_RING_RX_TAIL_REG 0x80018
56 #define HCLGE_RING_RX_HEAD_REG 0x8001C
57 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020
58 #define HCLGE_RING_RX_OFFSET_REG 0x80024
59 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
60 #define HCLGE_RING_RX_STASH_REG 0x80030
61 #define HCLGE_RING_RX_BD_ERR_REG 0x80034
62 #define HCLGE_RING_TX_ADDR_L_REG 0x80040
63 #define HCLGE_RING_TX_ADDR_H_REG 0x80044
64 #define HCLGE_RING_TX_BD_NUM_REG 0x80048
65 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C
66 #define HCLGE_RING_TX_TC_REG 0x80050
67 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054
68 #define HCLGE_RING_TX_TAIL_REG 0x80058
69 #define HCLGE_RING_TX_HEAD_REG 0x8005C
70 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060
71 #define HCLGE_RING_TX_OFFSET_REG 0x80064
72 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068
73 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
74 #define HCLGE_RING_TX_BD_ERR_REG 0x80074
75 #define HCLGE_RING_EN_REG 0x80090
76
77 /* bar registers for tqp interrupt */
78 #define HCLGE_TQP_INTR_CTRL_REG 0x20000
79 #define HCLGE_TQP_INTR_GL0_REG 0x20100
80 #define HCLGE_TQP_INTR_GL1_REG 0x20200
81 #define HCLGE_TQP_INTR_GL2_REG 0x20300
82 #define HCLGE_TQP_INTR_RL_REG 0x20900
83
84 #define HCLGE_RSS_IND_TBL_SIZE 512
85
86 #define HCLGE_RSS_TC_SIZE_0 1
87 #define HCLGE_RSS_TC_SIZE_1 2
88 #define HCLGE_RSS_TC_SIZE_2 4
89 #define HCLGE_RSS_TC_SIZE_3 8
90 #define HCLGE_RSS_TC_SIZE_4 16
91 #define HCLGE_RSS_TC_SIZE_5 32
92 #define HCLGE_RSS_TC_SIZE_6 64
93 #define HCLGE_RSS_TC_SIZE_7 128
94
95 #define HCLGE_UMV_TBL_SIZE 3072
96 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
97 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
98
99 #define HCLGE_TQP_RESET_TRY_TIMES 200
100
101 #define HCLGE_PHY_PAGE_MDIX 0
102 #define HCLGE_PHY_PAGE_COPPER 0
103
104 /* Page Selection Reg. */
105 #define HCLGE_PHY_PAGE_REG 22
106
107 /* Copper Specific Control Register */
108 #define HCLGE_PHY_CSC_REG 16
109
110 /* Copper Specific Status Register */
111 #define HCLGE_PHY_CSS_REG 17
112
113 #define HCLGE_PHY_MDIX_CTRL_S 5
114 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
115
116 #define HCLGE_PHY_MDIX_STATUS_B 6
117 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
118
119 #define HCLGE_GET_DFX_REG_TYPE_CNT 4
120
121 /* Factor used to calculate offset and bitmap of VF num */
122 #define HCLGE_VF_NUM_PER_CMD 64
123
124 #define HCLGE_MAX_QSET_NUM 1024
125
126 #define HCLGE_DBG_RESET_INFO_LEN 1024
127
128 enum HLCGE_PORT_TYPE {
129 HOST_PORT,
130 NETWORK_PORT
131 };
132
133 #define PF_VPORT_ID 0
134
135 #define HCLGE_PF_ID_S 0
136 #define HCLGE_PF_ID_M GENMASK(2, 0)
137 #define HCLGE_VF_ID_S 3
138 #define HCLGE_VF_ID_M GENMASK(10, 3)
139 #define HCLGE_PORT_TYPE_B 11
140 #define HCLGE_NETWORK_PORT_ID_S 0
141 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
142
143 /* Reset related Registers */
144 #define HCLGE_PF_OTHER_INT_REG 0x20600
145 #define HCLGE_MISC_RESET_STS_REG 0x20700
146 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
147 #define HCLGE_GLOBAL_RESET_REG 0x20A00
148 #define HCLGE_GLOBAL_RESET_BIT 0
149 #define HCLGE_CORE_RESET_BIT 1
150 #define HCLGE_IMP_RESET_BIT 2
151 #define HCLGE_RESET_INT_M GENMASK(7, 5)
152 #define HCLGE_FUN_RST_ING 0x20C00
153 #define HCLGE_FUN_RST_ING_B 0
154
155 /* Vector0 register bits define */
156 #define HCLGE_VECTOR0_REG_PTP_INT_B 0
157 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
158 #define HCLGE_VECTOR0_CORERESET_INT_B 6
159 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
160
161 /* Vector0 interrupt CMDQ event source register(RW) */
162 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
163 /* CMDQ register bits for RX event(=MBX event) */
164 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
165
166 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1
167 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
168 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
169 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U
170 #define HCLGE_TRIGGER_IMP_RESET_B 7U
171
172 #define HCLGE_TQP_MEM_SIZE 0x10000
173 #define HCLGE_MEM_BAR 4
174 /* in the bar4, the first half is for roce, and the second half is for nic */
175 #define HCLGE_NIC_MEM_OFFSET(hdev) \
176 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1)
177 #define HCLGE_TQP_MEM_OFFSET(hdev, i) \
178 (HCLGE_NIC_MEM_OFFSET(hdev) + HCLGE_TQP_MEM_SIZE * (i))
179
180 #define HCLGE_MAC_DEFAULT_FRAME \
181 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
182 #define HCLGE_MAC_MIN_FRAME 64
183 #define HCLGE_MAC_MAX_FRAME 9728
184
185 #define HCLGE_SUPPORT_1G_BIT BIT(0)
186 #define HCLGE_SUPPORT_10G_BIT BIT(1)
187 #define HCLGE_SUPPORT_25G_BIT BIT(2)
188 #define HCLGE_SUPPORT_50G_BIT BIT(3)
189 #define HCLGE_SUPPORT_100G_BIT BIT(4)
190 /* to be compatible with exsit board */
191 #define HCLGE_SUPPORT_40G_BIT BIT(5)
192 #define HCLGE_SUPPORT_100M_BIT BIT(6)
193 #define HCLGE_SUPPORT_10M_BIT BIT(7)
194 #define HCLGE_SUPPORT_200G_BIT BIT(8)
195 #define HCLGE_SUPPORT_GE \
196 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
197
198 enum HCLGE_DEV_STATE {
199 HCLGE_STATE_REINITING,
200 HCLGE_STATE_DOWN,
201 HCLGE_STATE_DISABLED,
202 HCLGE_STATE_REMOVING,
203 HCLGE_STATE_NIC_REGISTERED,
204 HCLGE_STATE_ROCE_REGISTERED,
205 HCLGE_STATE_SERVICE_INITED,
206 HCLGE_STATE_RST_SERVICE_SCHED,
207 HCLGE_STATE_RST_HANDLING,
208 HCLGE_STATE_MBX_SERVICE_SCHED,
209 HCLGE_STATE_MBX_HANDLING,
210 HCLGE_STATE_ERR_SERVICE_SCHED,
211 HCLGE_STATE_STATISTICS_UPDATING,
212 HCLGE_STATE_LINK_UPDATING,
213 HCLGE_STATE_RST_FAIL,
214 HCLGE_STATE_FD_TBL_CHANGED,
215 HCLGE_STATE_FD_CLEAR_ALL,
216 HCLGE_STATE_FD_USER_DEF_CHANGED,
217 HCLGE_STATE_PTP_EN,
218 HCLGE_STATE_PTP_TX_HANDLING,
219 HCLGE_STATE_MAX
220 };
221
222 enum hclge_evt_cause {
223 HCLGE_VECTOR0_EVENT_RST,
224 HCLGE_VECTOR0_EVENT_MBX,
225 HCLGE_VECTOR0_EVENT_ERR,
226 HCLGE_VECTOR0_EVENT_PTP,
227 HCLGE_VECTOR0_EVENT_OTHER,
228 };
229
230 enum HCLGE_MAC_SPEED {
231 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */
232 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
233 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
234 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
235 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
236 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
237 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
238 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
239 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
240 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
241 };
242
243 enum HCLGE_MAC_DUPLEX {
244 HCLGE_MAC_HALF,
245 HCLGE_MAC_FULL
246 };
247
248 #define QUERY_SFP_SPEED 0
249 #define QUERY_ACTIVE_SPEED 1
250
251 struct hclge_mac {
252 u8 mac_id;
253 u8 phy_addr;
254 u8 flag;
255 u8 media_type; /* port media type, e.g. fibre/copper/backplane */
256 u8 mac_addr[ETH_ALEN];
257 u8 autoneg;
258 u8 duplex;
259 u8 support_autoneg;
260 u8 speed_type; /* 0: sfp speed, 1: active speed */
261 u32 speed;
262 u32 max_speed;
263 u32 speed_ability; /* speed ability supported by current media */
264 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
265 u32 fec_mode; /* active fec mode */
266 u32 user_fec_mode;
267 u32 fec_ability;
268 int link; /* store the link status of mac & phy (if phy exists) */
269 struct phy_device *phydev;
270 struct mii_bus *mdio_bus;
271 phy_interface_t phy_if;
272 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
273 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
274 };
275
276 struct hclge_hw {
277 struct hclge_comm_hw hw;
278 struct hclge_mac mac;
279 int num_vec;
280 };
281
282 enum hclge_fc_mode {
283 HCLGE_FC_NONE,
284 HCLGE_FC_RX_PAUSE,
285 HCLGE_FC_TX_PAUSE,
286 HCLGE_FC_FULL,
287 HCLGE_FC_PFC,
288 HCLGE_FC_DEFAULT
289 };
290
291 #define HCLGE_FILTER_TYPE_VF 0
292 #define HCLGE_FILTER_TYPE_PORT 1
293 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
294 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
295 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
296 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)
297 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)
298 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \
299 | HCLGE_FILTER_FE_ROCE_EGRESS_B)
300 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \
301 | HCLGE_FILTER_FE_ROCE_INGRESS_B)
302
303 enum hclge_vlan_fltr_cap {
304 HCLGE_VLAN_FLTR_DEF,
305 HCLGE_VLAN_FLTR_CAN_MDF,
306 };
307 enum hclge_link_fail_code {
308 HCLGE_LF_NORMAL,
309 HCLGE_LF_REF_CLOCK_LOST,
310 HCLGE_LF_XSFP_TX_DISABLE,
311 HCLGE_LF_XSFP_ABSENT,
312 };
313
314 #define HCLGE_LINK_STATUS_DOWN 0
315 #define HCLGE_LINK_STATUS_UP 1
316
317 #define HCLGE_PG_NUM 4
318 #define HCLGE_SCH_MODE_SP 0
319 #define HCLGE_SCH_MODE_DWRR 1
320 struct hclge_pg_info {
321 u8 pg_id;
322 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
323 u8 tc_bit_map;
324 u32 bw_limit;
325 u8 tc_dwrr[HNAE3_MAX_TC];
326 };
327
328 struct hclge_tc_info {
329 u8 tc_id;
330 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
331 u8 pgid;
332 u32 bw_limit;
333 };
334
335 struct hclge_cfg {
336 u8 tc_num;
337 u8 vlan_fliter_cap;
338 u16 tqp_desc_num;
339 u16 rx_buf_len;
340 u16 vf_rss_size_max;
341 u16 pf_rss_size_max;
342 u8 phy_addr;
343 u8 media_type;
344 u8 mac_addr[ETH_ALEN];
345 u8 default_speed;
346 u32 numa_node_map;
347 u32 tx_spare_buf_size;
348 u16 speed_ability;
349 u16 umv_space;
350 };
351
352 struct hclge_tm_info {
353 u8 num_tc;
354 u8 num_pg; /* It must be 1 if vNET-Base schd */
355 u8 pg_dwrr[HCLGE_PG_NUM];
356 u8 prio_tc[HNAE3_MAX_USER_PRIO];
357 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
358 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
359 enum hclge_fc_mode fc_mode;
360 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
361 u8 pfc_en; /* PFC enabled or not for user priority */
362 };
363
364 /* max number of mac statistics on each version */
365 #define HCLGE_MAC_STATS_MAX_NUM_V1 87
366 #define HCLGE_MAC_STATS_MAX_NUM_V2 105
367
368 struct hclge_comm_stats_str {
369 char desc[ETH_GSTRING_LEN];
370 u32 stats_num;
371 unsigned long offset;
372 };
373
374 /* mac stats ,opcode id: 0x0032 */
375 struct hclge_mac_stats {
376 u64 mac_tx_mac_pause_num;
377 u64 mac_rx_mac_pause_num;
378 u64 rsv0;
379 u64 mac_tx_pfc_pri0_pkt_num;
380 u64 mac_tx_pfc_pri1_pkt_num;
381 u64 mac_tx_pfc_pri2_pkt_num;
382 u64 mac_tx_pfc_pri3_pkt_num;
383 u64 mac_tx_pfc_pri4_pkt_num;
384 u64 mac_tx_pfc_pri5_pkt_num;
385 u64 mac_tx_pfc_pri6_pkt_num;
386 u64 mac_tx_pfc_pri7_pkt_num;
387 u64 mac_rx_pfc_pri0_pkt_num;
388 u64 mac_rx_pfc_pri1_pkt_num;
389 u64 mac_rx_pfc_pri2_pkt_num;
390 u64 mac_rx_pfc_pri3_pkt_num;
391 u64 mac_rx_pfc_pri4_pkt_num;
392 u64 mac_rx_pfc_pri5_pkt_num;
393 u64 mac_rx_pfc_pri6_pkt_num;
394 u64 mac_rx_pfc_pri7_pkt_num;
395 u64 mac_tx_total_pkt_num;
396 u64 mac_tx_total_oct_num;
397 u64 mac_tx_good_pkt_num;
398 u64 mac_tx_bad_pkt_num;
399 u64 mac_tx_good_oct_num;
400 u64 mac_tx_bad_oct_num;
401 u64 mac_tx_uni_pkt_num;
402 u64 mac_tx_multi_pkt_num;
403 u64 mac_tx_broad_pkt_num;
404 u64 mac_tx_undersize_pkt_num;
405 u64 mac_tx_oversize_pkt_num;
406 u64 mac_tx_64_oct_pkt_num;
407 u64 mac_tx_65_127_oct_pkt_num;
408 u64 mac_tx_128_255_oct_pkt_num;
409 u64 mac_tx_256_511_oct_pkt_num;
410 u64 mac_tx_512_1023_oct_pkt_num;
411 u64 mac_tx_1024_1518_oct_pkt_num;
412 u64 mac_tx_1519_2047_oct_pkt_num;
413 u64 mac_tx_2048_4095_oct_pkt_num;
414 u64 mac_tx_4096_8191_oct_pkt_num;
415 u64 rsv1;
416 u64 mac_tx_8192_9216_oct_pkt_num;
417 u64 mac_tx_9217_12287_oct_pkt_num;
418 u64 mac_tx_12288_16383_oct_pkt_num;
419 u64 mac_tx_1519_max_good_oct_pkt_num;
420 u64 mac_tx_1519_max_bad_oct_pkt_num;
421
422 u64 mac_rx_total_pkt_num;
423 u64 mac_rx_total_oct_num;
424 u64 mac_rx_good_pkt_num;
425 u64 mac_rx_bad_pkt_num;
426 u64 mac_rx_good_oct_num;
427 u64 mac_rx_bad_oct_num;
428 u64 mac_rx_uni_pkt_num;
429 u64 mac_rx_multi_pkt_num;
430 u64 mac_rx_broad_pkt_num;
431 u64 mac_rx_undersize_pkt_num;
432 u64 mac_rx_oversize_pkt_num;
433 u64 mac_rx_64_oct_pkt_num;
434 u64 mac_rx_65_127_oct_pkt_num;
435 u64 mac_rx_128_255_oct_pkt_num;
436 u64 mac_rx_256_511_oct_pkt_num;
437 u64 mac_rx_512_1023_oct_pkt_num;
438 u64 mac_rx_1024_1518_oct_pkt_num;
439 u64 mac_rx_1519_2047_oct_pkt_num;
440 u64 mac_rx_2048_4095_oct_pkt_num;
441 u64 mac_rx_4096_8191_oct_pkt_num;
442 u64 rsv2;
443 u64 mac_rx_8192_9216_oct_pkt_num;
444 u64 mac_rx_9217_12287_oct_pkt_num;
445 u64 mac_rx_12288_16383_oct_pkt_num;
446 u64 mac_rx_1519_max_good_oct_pkt_num;
447 u64 mac_rx_1519_max_bad_oct_pkt_num;
448
449 u64 mac_tx_fragment_pkt_num;
450 u64 mac_tx_undermin_pkt_num;
451 u64 mac_tx_jabber_pkt_num;
452 u64 mac_tx_err_all_pkt_num;
453 u64 mac_tx_from_app_good_pkt_num;
454 u64 mac_tx_from_app_bad_pkt_num;
455 u64 mac_rx_fragment_pkt_num;
456 u64 mac_rx_undermin_pkt_num;
457 u64 mac_rx_jabber_pkt_num;
458 u64 mac_rx_fcs_err_pkt_num;
459 u64 mac_rx_send_app_good_pkt_num;
460 u64 mac_rx_send_app_bad_pkt_num;
461 u64 mac_tx_pfc_pause_pkt_num;
462 u64 mac_rx_pfc_pause_pkt_num;
463 u64 mac_tx_ctrl_pkt_num;
464 u64 mac_rx_ctrl_pkt_num;
465
466 /* duration of pfc */
467 u64 mac_tx_pfc_pri0_xoff_time;
468 u64 mac_tx_pfc_pri1_xoff_time;
469 u64 mac_tx_pfc_pri2_xoff_time;
470 u64 mac_tx_pfc_pri3_xoff_time;
471 u64 mac_tx_pfc_pri4_xoff_time;
472 u64 mac_tx_pfc_pri5_xoff_time;
473 u64 mac_tx_pfc_pri6_xoff_time;
474 u64 mac_tx_pfc_pri7_xoff_time;
475 u64 mac_rx_pfc_pri0_xoff_time;
476 u64 mac_rx_pfc_pri1_xoff_time;
477 u64 mac_rx_pfc_pri2_xoff_time;
478 u64 mac_rx_pfc_pri3_xoff_time;
479 u64 mac_rx_pfc_pri4_xoff_time;
480 u64 mac_rx_pfc_pri5_xoff_time;
481 u64 mac_rx_pfc_pri6_xoff_time;
482 u64 mac_rx_pfc_pri7_xoff_time;
483
484 /* duration of pause */
485 u64 mac_tx_pause_xoff_time;
486 u64 mac_rx_pause_xoff_time;
487 };
488
489 #define HCLGE_STATS_TIMER_INTERVAL 300UL
490
491 struct hclge_vlan_type_cfg {
492 u16 rx_ot_fst_vlan_type;
493 u16 rx_ot_sec_vlan_type;
494 u16 rx_in_fst_vlan_type;
495 u16 rx_in_sec_vlan_type;
496 u16 tx_ot_vlan_type;
497 u16 tx_in_vlan_type;
498 };
499
500 enum HCLGE_FD_MODE {
501 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
502 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
503 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
504 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
505 };
506
507 enum HCLGE_FD_KEY_TYPE {
508 HCLGE_FD_KEY_BASE_ON_PTYPE,
509 HCLGE_FD_KEY_BASE_ON_TUPLE,
510 };
511
512 enum HCLGE_FD_STAGE {
513 HCLGE_FD_STAGE_1,
514 HCLGE_FD_STAGE_2,
515 MAX_STAGE_NUM,
516 };
517
518 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
519 * INNER_XXX indicate tuples in tunneled header of tunnel packet or
520 * tuples of non-tunnel packet
521 */
522 enum HCLGE_FD_TUPLE {
523 OUTER_DST_MAC,
524 OUTER_SRC_MAC,
525 OUTER_VLAN_TAG_FST,
526 OUTER_VLAN_TAG_SEC,
527 OUTER_ETH_TYPE,
528 OUTER_L2_RSV,
529 OUTER_IP_TOS,
530 OUTER_IP_PROTO,
531 OUTER_SRC_IP,
532 OUTER_DST_IP,
533 OUTER_L3_RSV,
534 OUTER_SRC_PORT,
535 OUTER_DST_PORT,
536 OUTER_L4_RSV,
537 OUTER_TUN_VNI,
538 OUTER_TUN_FLOW_ID,
539 INNER_DST_MAC,
540 INNER_SRC_MAC,
541 INNER_VLAN_TAG_FST,
542 INNER_VLAN_TAG_SEC,
543 INNER_ETH_TYPE,
544 INNER_L2_RSV,
545 INNER_IP_TOS,
546 INNER_IP_PROTO,
547 INNER_SRC_IP,
548 INNER_DST_IP,
549 INNER_L3_RSV,
550 INNER_SRC_PORT,
551 INNER_DST_PORT,
552 INNER_L4_RSV,
553 MAX_TUPLE,
554 };
555
556 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \
557 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV))
558
559 enum HCLGE_FD_META_DATA {
560 PACKET_TYPE_ID,
561 IP_FRAGEMENT,
562 ROCE_TYPE,
563 NEXT_KEY,
564 VLAN_NUMBER,
565 SRC_VPORT,
566 DST_VPORT,
567 TUNNEL_PACKET,
568 MAX_META_DATA,
569 };
570
571 enum HCLGE_FD_KEY_OPT {
572 KEY_OPT_U8,
573 KEY_OPT_LE16,
574 KEY_OPT_LE32,
575 KEY_OPT_MAC,
576 KEY_OPT_IP,
577 KEY_OPT_VNI,
578 };
579
580 struct key_info {
581 u8 key_type;
582 u8 key_length; /* use bit as unit */
583 enum HCLGE_FD_KEY_OPT key_opt;
584 int offset;
585 int moffset;
586 };
587
588 #define MAX_KEY_LENGTH 400
589 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
590 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
591 #define MAX_META_DATA_LENGTH 32
592
593 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000
594 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0)
595 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0)
596 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0)
597
598 /* assigned by firmware, the real filter number for each pf may be less */
599 #define MAX_FD_FILTER_NUM 4096
600 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
601
602 #define hclge_read_dev(a, reg) \
603 hclge_comm_read_reg((a)->hw.io_base, reg)
604 #define hclge_write_dev(a, reg, value) \
605 hclge_comm_write_reg((a)->hw.io_base, reg, value)
606
607 enum HCLGE_FD_ACTIVE_RULE_TYPE {
608 HCLGE_FD_RULE_NONE,
609 HCLGE_FD_ARFS_ACTIVE,
610 HCLGE_FD_EP_ACTIVE,
611 HCLGE_FD_TC_FLOWER_ACTIVE,
612 };
613
614 enum HCLGE_FD_PACKET_TYPE {
615 NIC_PACKET,
616 ROCE_PACKET,
617 };
618
619 enum HCLGE_FD_ACTION {
620 HCLGE_FD_ACTION_SELECT_QUEUE,
621 HCLGE_FD_ACTION_DROP_PACKET,
622 HCLGE_FD_ACTION_SELECT_TC,
623 };
624
625 enum HCLGE_FD_NODE_STATE {
626 HCLGE_FD_TO_ADD,
627 HCLGE_FD_TO_DEL,
628 HCLGE_FD_ACTIVE,
629 HCLGE_FD_DELETED,
630 };
631
632 enum HCLGE_FD_USER_DEF_LAYER {
633 HCLGE_FD_USER_DEF_NONE,
634 HCLGE_FD_USER_DEF_L2,
635 HCLGE_FD_USER_DEF_L3,
636 HCLGE_FD_USER_DEF_L4,
637 };
638
639 #define HCLGE_FD_USER_DEF_LAYER_NUM 3
640 struct hclge_fd_user_def_cfg {
641 u16 ref_cnt;
642 u16 offset;
643 };
644
645 struct hclge_fd_user_def_info {
646 enum HCLGE_FD_USER_DEF_LAYER layer;
647 u16 data;
648 u16 data_mask;
649 u16 offset;
650 };
651
652 struct hclge_fd_key_cfg {
653 u8 key_sel;
654 u8 inner_sipv6_word_en;
655 u8 inner_dipv6_word_en;
656 u8 outer_sipv6_word_en;
657 u8 outer_dipv6_word_en;
658 u32 tuple_active;
659 u32 meta_data_active;
660 };
661
662 struct hclge_fd_cfg {
663 u8 fd_mode;
664 u16 max_key_length; /* use bit as unit */
665 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
666 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
667 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
668 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM];
669 };
670
671 #define IPV4_INDEX 3
672 #define IPV6_SIZE 4
673 struct hclge_fd_rule_tuples {
674 u8 src_mac[ETH_ALEN];
675 u8 dst_mac[ETH_ALEN];
676 /* Be compatible for ip address of both ipv4 and ipv6.
677 * For ipv4 address, we store it in src/dst_ip[3].
678 */
679 u32 src_ip[IPV6_SIZE];
680 u32 dst_ip[IPV6_SIZE];
681 u16 src_port;
682 u16 dst_port;
683 u16 vlan_tag1;
684 u16 ether_proto;
685 u16 l2_user_def;
686 u16 l3_user_def;
687 u32 l4_user_def;
688 u8 ip_tos;
689 u8 ip_proto;
690 };
691
692 struct hclge_fd_rule {
693 struct hlist_node rule_node;
694 struct hclge_fd_rule_tuples tuples;
695 struct hclge_fd_rule_tuples tuples_mask;
696 u32 unused_tuple;
697 u32 flow_type;
698 union {
699 struct {
700 unsigned long cookie;
701 u8 tc;
702 } cls_flower;
703 struct {
704 u16 flow_id; /* only used for arfs */
705 } arfs;
706 struct {
707 struct hclge_fd_user_def_info user_def;
708 } ep;
709 };
710 u16 queue_id;
711 u16 vf_id;
712 u16 location;
713 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
714 enum HCLGE_FD_NODE_STATE state;
715 u8 action;
716 };
717
718 struct hclge_fd_ad_data {
719 u16 ad_id;
720 u8 drop_packet;
721 u8 forward_to_direct_queue;
722 u16 queue_id;
723 u8 use_counter;
724 u8 counter_id;
725 u8 use_next_stage;
726 u8 write_rule_id_to_bd;
727 u8 next_input_key;
728 u16 rule_id;
729 u16 tc_size;
730 u8 override_tc;
731 };
732
733 enum HCLGE_MAC_NODE_STATE {
734 HCLGE_MAC_TO_ADD,
735 HCLGE_MAC_TO_DEL,
736 HCLGE_MAC_ACTIVE
737 };
738
739 struct hclge_mac_node {
740 struct list_head node;
741 enum HCLGE_MAC_NODE_STATE state;
742 u8 mac_addr[ETH_ALEN];
743 };
744
745 enum HCLGE_MAC_ADDR_TYPE {
746 HCLGE_MAC_ADDR_UC,
747 HCLGE_MAC_ADDR_MC
748 };
749
750 struct hclge_vport_vlan_cfg {
751 struct list_head node;
752 int hd_tbl_status;
753 u16 vlan_id;
754 };
755
756 struct hclge_rst_stats {
757 u32 reset_done_cnt; /* the number of reset has completed */
758 u32 hw_reset_done_cnt; /* the number of HW reset has completed */
759 u32 pf_rst_cnt; /* the number of PF reset */
760 u32 flr_rst_cnt; /* the number of FLR */
761 u32 global_rst_cnt; /* the number of GLOBAL */
762 u32 imp_rst_cnt; /* the number of IMP reset */
763 u32 reset_cnt; /* the number of reset */
764 u32 reset_fail_cnt; /* the number of reset fail */
765 };
766
767 /* time and register status when mac tunnel interruption occur */
768 struct hclge_mac_tnl_stats {
769 u64 time;
770 u32 status;
771 };
772
773 #define HCLGE_RESET_INTERVAL (10 * HZ)
774 #define HCLGE_WAIT_RESET_DONE 100
775
776 #pragma pack(1)
777 struct hclge_vf_vlan_cfg {
778 u8 mbx_cmd;
779 u8 subcode;
780 union {
781 struct {
782 u8 is_kill;
783 __le16 vlan;
784 __le16 proto;
785 };
786 u8 enable;
787 };
788 };
789
790 #pragma pack()
791
792 /* For each bit of TCAM entry, it uses a pair of 'x' and
793 * 'y' to indicate which value to match, like below:
794 * ----------------------------------
795 * | bit x | bit y | search value |
796 * ----------------------------------
797 * | 0 | 0 | always hit |
798 * ----------------------------------
799 * | 1 | 0 | match '0' |
800 * ----------------------------------
801 * | 0 | 1 | match '1' |
802 * ----------------------------------
803 * | 1 | 1 | invalid |
804 * ----------------------------------
805 * Then for input key(k) and mask(v), we can calculate the value by
806 * the formulae:
807 * x = (~k) & v
808 * y = (k ^ ~v) & k
809 */
810 #define calc_x(x, k, v) (x = ~(k) & (v))
811 #define calc_y(y, k, v) \
812 do { \
813 const typeof(k) _k_ = (k); \
814 const typeof(v) _v_ = (v); \
815 (y) = (_k_ ^ ~_v_) & (_k_); \
816 } while (0)
817
818 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
819 #define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset)))
820
821 #define HCLGE_MAC_TNL_LOG_SIZE 8
822 #define HCLGE_VPORT_NUM 256
823 struct hclge_dev {
824 struct pci_dev *pdev;
825 struct hnae3_ae_dev *ae_dev;
826 struct hclge_hw hw;
827 struct hclge_misc_vector misc_vector;
828 struct hclge_mac_stats mac_stats;
829 unsigned long state;
830 unsigned long flr_state;
831 unsigned long last_reset_time;
832
833 enum hnae3_reset_type reset_type;
834 enum hnae3_reset_type reset_level;
835 unsigned long default_reset_request;
836 unsigned long reset_request; /* reset has been requested */
837 unsigned long reset_pending; /* client rst is pending to be served */
838 struct hclge_rst_stats rst_stats;
839 struct semaphore reset_sem; /* protect reset process */
840 u32 fw_version;
841 u16 num_tqps; /* Num task queue pairs of this PF */
842 u16 num_req_vfs; /* Num VFs requested for this PF */
843
844 u16 base_tqp_pid; /* Base task tqp physical id of this PF */
845 u16 alloc_rss_size; /* Allocated RSS task queue */
846 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */
847 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */
848 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */
849
850 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
851 u16 num_alloc_vport; /* Num vports this driver supports */
852 u32 numa_node_mask;
853 u16 rx_buf_len;
854 u16 num_tx_desc; /* desc num of per tx queue */
855 u16 num_rx_desc; /* desc num of per rx queue */
856 u8 hw_tc_map;
857 enum hclge_fc_mode fc_mode_last_time;
858 u8 support_sfp_query;
859
860 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
861 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
862 u8 tx_sch_mode;
863 u8 tc_max;
864 u8 pfc_max;
865
866 u8 default_up;
867 u8 dcbx_cap;
868 struct hclge_tm_info tm_info;
869
870 u16 num_msi;
871 u16 num_msi_left;
872 u16 num_msi_used;
873 u16 *vector_status;
874 int *vector_irq;
875 u16 num_nic_msi; /* Num of nic vectors for this PF */
876 u16 num_roce_msi; /* Num of roce vectors for this PF */
877
878 unsigned long service_timer_period;
879 unsigned long service_timer_previous;
880 struct timer_list reset_timer;
881 struct delayed_work service_task;
882
883 bool cur_promisc;
884 int num_alloc_vfs; /* Actual number of VFs allocated */
885
886 struct hclge_comm_tqp *htqp;
887 struct hclge_vport *vport;
888
889 struct dentry *hclge_dbgfs;
890
891 struct hnae3_client *nic_client;
892 struct hnae3_client *roce_client;
893
894 #define HCLGE_FLAG_MAIN BIT(0)
895 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
896 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
897 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
898 u32 flag;
899
900 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
901 u32 tx_buf_size; /* Tx buffer size for each TC */
902 u32 dv_buf_size; /* Dv buffer size for each TC */
903
904 u32 mps; /* Max packet size */
905 /* vport_lock protect resource shared by vports */
906 struct mutex vport_lock;
907
908 struct hclge_vlan_type_cfg vlan_type_cfg;
909
910 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
911 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
912
913 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
914
915 struct hclge_fd_cfg fd_cfg;
916 struct hlist_head fd_rule_list;
917 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
918 u16 hclge_fd_rule_num;
919 unsigned long serv_processed_cnt;
920 unsigned long last_serv_processed;
921 unsigned long last_rst_scheduled;
922 unsigned long last_mbx_scheduled;
923 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
924 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
925 u8 fd_en;
926 bool gro_en;
927
928 u16 wanted_umv_size;
929 /* max available unicast mac vlan space */
930 u16 max_umv_size;
931 /* private unicast mac vlan space, it's same for PF and its VFs */
932 u16 priv_umv_size;
933 /* unicast mac vlan space shared by PF and its VFs */
934 u16 share_umv_size;
935 /* multicast mac address number used by PF and its VFs */
936 u16 used_mc_mac_num;
937
938 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
939 HCLGE_MAC_TNL_LOG_SIZE);
940
941 struct hclge_ptp *ptp;
942 struct devlink *devlink;
943 struct hclge_comm_rss_cfg rss_cfg;
944 };
945
946 /* VPort level vlan tag configuration for TX direction */
947 struct hclge_tx_vtag_cfg {
948 bool accept_tag1; /* Whether accept tag1 packet from host */
949 bool accept_untag1; /* Whether accept untag1 packet from host */
950 bool accept_tag2;
951 bool accept_untag2;
952 bool insert_tag1_en; /* Whether insert inner vlan tag */
953 bool insert_tag2_en; /* Whether insert outer vlan tag */
954 u16 default_tag1; /* The default inner vlan tag to insert */
955 u16 default_tag2; /* The default outer vlan tag to insert */
956 bool tag_shift_mode_en;
957 };
958
959 /* VPort level vlan tag configuration for RX direction */
960 struct hclge_rx_vtag_cfg {
961 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
962 bool strip_tag1_en; /* Whether strip inner vlan tag */
963 bool strip_tag2_en; /* Whether strip outer vlan tag */
964 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */
965 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */
966 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */
967 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */
968 };
969
970 enum HCLGE_VPORT_STATE {
971 HCLGE_VPORT_STATE_ALIVE,
972 HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
973 HCLGE_VPORT_STATE_PROMISC_CHANGE,
974 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
975 HCLGE_VPORT_STATE_MAX
976 };
977
978 struct hclge_vlan_info {
979 u16 vlan_proto; /* so far support 802.1Q only */
980 u16 qos;
981 u16 vlan_tag;
982 };
983
984 struct hclge_port_base_vlan_config {
985 u16 state;
986 bool tbl_sta;
987 struct hclge_vlan_info vlan_info;
988 struct hclge_vlan_info old_vlan_info;
989 };
990
991 struct hclge_vf_info {
992 int link_state;
993 u8 mac[ETH_ALEN];
994 u32 spoofchk;
995 u32 max_tx_rate;
996 u32 trusted;
997 u8 request_uc_en;
998 u8 request_mc_en;
999 u8 request_bc_en;
1000 };
1001
1002 struct hclge_vport {
1003 u16 alloc_tqps; /* Allocated Tx/Rx queues */
1004
1005 u16 qs_offset;
1006 u32 bw_limit; /* VSI BW Limit (0 = disabled) */
1007 u8 dwrr;
1008
1009 bool req_vlan_fltr_en;
1010 bool cur_vlan_fltr_en;
1011 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
1012 struct hclge_port_base_vlan_config port_base_vlan_cfg;
1013 struct hclge_tx_vtag_cfg txvlan_cfg;
1014 struct hclge_rx_vtag_cfg rxvlan_cfg;
1015
1016 u16 used_umv_num;
1017
1018 u16 vport_id;
1019 struct hclge_dev *back; /* Back reference to associated dev */
1020 struct hnae3_handle nic;
1021 struct hnae3_handle roce;
1022
1023 unsigned long state;
1024 unsigned long last_active_jiffies;
1025 u32 mps; /* Max packet size */
1026 struct hclge_vf_info vf_info;
1027
1028 u8 overflow_promisc_flags;
1029 u8 last_promisc_flags;
1030
1031 spinlock_t mac_list_lock; /* protect mac address need to add/detele */
1032 struct list_head uc_mac_list; /* Store VF unicast table */
1033 struct list_head mc_mac_list; /* Store VF multicast table */
1034
1035 struct list_head vlan_list; /* Store VF vlan table */
1036 };
1037
1038 struct hclge_speed_bit_map {
1039 u32 speed;
1040 u32 speed_bit;
1041 };
1042
1043 struct hclge_mac_speed_map {
1044 u32 speed_drv; /* speed defined in driver */
1045 u32 speed_fw; /* speed defined in firmware */
1046 };
1047
1048 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
1049 bool en_mc_pmc, bool en_bc_pmc);
1050 int hclge_add_uc_addr_common(struct hclge_vport *vport,
1051 const unsigned char *addr);
1052 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
1053 const unsigned char *addr);
1054 int hclge_add_mc_addr_common(struct hclge_vport *vport,
1055 const unsigned char *addr);
1056 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
1057 const unsigned char *addr);
1058
1059 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
1060 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
1061 int vector_id, bool en,
1062 struct hnae3_ring_chain_node *ring_chain);
1063
hclge_get_queue_id(struct hnae3_queue * queue)1064 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
1065 {
1066 struct hclge_comm_tqp *tqp =
1067 container_of(queue, struct hclge_comm_tqp, q);
1068
1069 return tqp->index;
1070 }
1071
1072 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
1073 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
1074 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
1075 u16 vlan_id, bool is_kill);
1076 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
1077
1078 int hclge_buffer_alloc(struct hclge_dev *hdev);
1079 int hclge_rss_init_hw(struct hclge_dev *hdev);
1080
1081 void hclge_mbx_handler(struct hclge_dev *hdev);
1082 int hclge_reset_tqp(struct hnae3_handle *handle);
1083 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
1084 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
1085 int hclge_vport_start(struct hclge_vport *vport);
1086 void hclge_vport_stop(struct hclge_vport *vport);
1087 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
1088 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
1089 char *buf, int len);
1090 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
1091 int hclge_notify_client(struct hclge_dev *hdev,
1092 enum hnae3_reset_notify_type type);
1093 int hclge_update_mac_list(struct hclge_vport *vport,
1094 enum HCLGE_MAC_NODE_STATE state,
1095 enum HCLGE_MAC_ADDR_TYPE mac_type,
1096 const unsigned char *addr);
1097 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
1098 const u8 *old_addr, const u8 *new_addr);
1099 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
1100 enum HCLGE_MAC_ADDR_TYPE mac_type);
1101 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1102 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1103 void hclge_restore_mac_table_common(struct hclge_vport *vport);
1104 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev);
1105 void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
1106 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
1107 struct hclge_vlan_info *vlan_info);
1108 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1109 u16 state,
1110 struct hclge_vlan_info *vlan_info);
1111 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1112 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1113 struct hclge_desc *desc);
1114 void hclge_report_hw_error(struct hclge_dev *hdev,
1115 enum hnae3_hw_error_type type);
1116 void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
1117 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len);
1118 int hclge_push_vf_link_status(struct hclge_vport *vport);
1119 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);
1120 int hclge_mac_update_stats(struct hclge_dev *hdev);
1121 #endif
1122