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Searched refs:GICD_ICPENDR (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/tools/testing/selftests/kvm/include/aarch64/
Dgic_v3.h20 #define GICD_ICPENDR 0x0280 macro
/linux-5.19.10/include/linux/irqchip/
Darm-gic-v3.h26 #define GICD_ICPENDR 0x0280 macro
234 #define GICR_ICPENDR0 GICD_ICPENDR
/linux-5.19.10/tools/testing/selftests/kvm/lib/aarch64/
Dgic_v3.c258 gicv3_write_reg(intid, GICD_ICPENDR, 32, 1, 1); in gicv3_irq_clear_pending()
/linux-5.19.10/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst99 GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0. These registers behave
159 Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
/linux-5.19.10/drivers/irqchip/
Dirq-gic-v3.c312 case GICD_ICPENDR: in convert_offset_index()
414 reg = val ? GICD_ISPENDR : GICD_ICPENDR; in gic_irq_set_irqchip_state()
/linux-5.19.10/arch/arm64/kvm/vgic/
Dvgic-mmio-v3.c635 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,