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Searched refs:GENFC_WT__VSYNC_SEL_W__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h7156 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 macro
Ddce_8_0_sh_mask.h10634 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
Ddce_10_0_sh_mask.h11018 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
Ddce_11_0_sh_mask.h10830 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
Ddce_11_2_sh_mask.h12084 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
Ddce_12_0_sh_mask.h2182 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h219 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_1_0_sh_mask.h821 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_3_0_1_sh_mask.h316 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_3_1_2_sh_mask.h316 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_3_1_5_sh_mask.h5122 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_3_0_2_sh_mask.h232 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_3_1_6_sh_mask.h329 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_2_0_0_sh_mask.h232 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
Ddcn_3_0_0_sh_mask.h212 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro