Searched refs:GEN8_L3SQCREG4 (Results 1 – 8 of 8) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/i915/gt/ |
| D | intel_workarounds.c | 1713 whitelist_reg(w, GEN8_L3SQCREG4); in skl_whitelist_build()
1734 whitelist_reg(w, GEN8_L3SQCREG4); in kbl_whitelist_build()
2284 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2368 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2374 wa_write_clr_set(wal, GEN8_L3SQCREG4, in rcs_engine_wa_init()
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| D | intel_lrc.c | 1470 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1476 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1485 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
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| D | intel_gt_regs.h | 948 #define GEN8_L3SQCREG4 _MMIO(0xb118) macro
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| D | selftest_workarounds.c | 994 { GEN8_L3SQCREG4, 9 }, in pardon_reg()
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| /linux-5.19.10/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 109 {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
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| D | handlers.c | 737 GEN8_L3SQCREG4,//_MMIO(0xb118)
2540 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
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| D | cmd_parser.c | 921 if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) || in cmd_reg_handler()
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| /linux-5.19.10/drivers/gpu/drm/i915/ |
| D | intel_gvt_mmio_table.c | 819 MMIO_D(GEN8_L3SQCREG4); in iterate_bdw_plus_mmio()
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