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Searched refs:FW_BLC_SELF_EN (Results 1 – 5 of 5) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/gma500/
Dcdv_intel_display.c471 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
534 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()
Dpsb_intel_reg.h567 #define FW_BLC_SELF_EN (1<<15) macro
/linux-5.19.10/drivers/gpu/drm/i915/
Dintel_pm.c388 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
389 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()
401 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
402 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
403 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); in _intel_set_memory_cxsr()
6839 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
Di915_reg.h1088 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ macro
/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_display_debugfs.c89 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()