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Searched refs:FRQCR (Results 1 – 20 of 20) sorted by relevance

/linux-5.19.10/arch/sh/include/cpu-sh4/cpu/
Dfreq.h14 #define FRQCR 0xa4150000 macro
23 #define FRQCR 0xffc80000 macro
28 #define FRQCR 0xffc80000 macro
36 #define FRQCR FRQCRA macro
65 #define FRQCR 0xffc00000 macro
/linux-5.19.10/arch/sh/kernel/cpu/sh4a/
Dclock-sh7780.c24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
33 int idx = (__raw_readl(FRQCR) & 0x0003); in module_clk_recalc()
43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); in bus_clk_recalc()
53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); in cpu_clk_recalc()
76 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); in shyway_clk_recalc()
Dclock-sh7770.c21 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
30 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); in module_clk_recalc()
40 int idx = (__raw_readl(FRQCR) & 0x000f); in bus_clk_recalc()
50 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); in cpu_clk_recalc()
Dclock-sh7722.c18 #define FRQCR 0xa4150000 macro
71 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
114 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
115 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
116 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
117 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
118 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
119 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
Dclock-sh7763.c24 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; in master_clk_init()
33 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); in module_clk_recalc()
43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); in bus_clk_recalc()
70 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); in shyway_clk_recalc()
Dclock-sh7366.c16 #define FRQCR 0xa4150000 macro
68 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
112 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
113 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
114 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
115 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
116 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
117 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
Dclock-sh7343.c16 #define FRQCR 0xa4150000 macro
67 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
109 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
110 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
111 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
112 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
113 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
114 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
Dclock-sh7723.c19 #define FRQCR 0xa4150000 macro
72 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
115 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
116 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
117 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
118 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
119 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
120 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
Dclock-sh7757.c63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
/linux-5.19.10/arch/sh/kernel/cpu/sh3/
Dclock-sh7710.c26 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
35 int idx = (__raw_readw(FRQCR) & 0x0007); in module_clk_recalc()
45 int idx = (__raw_readw(FRQCR) & 0x0700) >> 8; in bus_clk_recalc()
55 int idx = (__raw_readw(FRQCR) & 0x0070) >> 4; in cpu_clk_recalc()
Dclock-sh7705.c32 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; in master_clk_init()
41 int idx = __raw_readw(FRQCR) & 0x0003; in module_clk_recalc()
51 int idx = (__raw_readw(FRQCR) & 0x0300) >> 8; in bus_clk_recalc()
61 int idx = (__raw_readw(FRQCR) & 0x0030) >> 4; in cpu_clk_recalc()
Dclock-sh3.c28 int frqcr = __raw_readw(FRQCR); in master_clk_init()
40 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
52 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
64 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
Dclock-sh7706.c24 int frqcr = __raw_readw(FRQCR); in master_clk_init()
36 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
48 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
60 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
Dclock-sh7709.c24 int frqcr = __raw_readw(FRQCR); in master_clk_init()
36 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
48 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
61 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
Dclock-sh7712.c23 int frqcr = __raw_readw(FRQCR); in master_clk_init()
35 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
47 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
/linux-5.19.10/arch/sh/kernel/cpu/sh4/
Dclock-sh4.c28 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
37 int idx = (__raw_readw(FRQCR) & 0x0007); in module_clk_recalc()
47 int idx = (__raw_readw(FRQCR) >> 3) & 0x0007; in bus_clk_recalc()
57 int idx = (__raw_readw(FRQCR) >> 6) & 0x0007; in cpu_clk_recalc()
/linux-5.19.10/arch/sh/boards/mach-hp6xx/
Dpm.c55 frqcr = __raw_readw(FRQCR); in pm_enter()
57 __raw_writew(frqcr, FRQCR); in pm_enter()
85 frqcr = __raw_readw(FRQCR); in pm_enter()
87 __raw_writew(frqcr, FRQCR); in pm_enter()
90 __raw_writew(frqcr, FRQCR); in pm_enter()
/linux-5.19.10/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c16 #define FRQCR 0xfffe0010 macro
44 return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1]; in pll_recalc()
82 [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
84 [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
Dclock-sh7269.c16 #define FRQCR 0xfffe0010 macro
110 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
112 [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
/linux-5.19.10/arch/sh/include/cpu-sh3/cpu/
Dfreq.h11 #define FRQCR 0xA415FF80 macro
13 #define FRQCR 0xffffff80 macro