Searched refs:EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (Results 1 – 1 of 1) sorted by relevance
59 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0) macro138 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6; in exynos4x12_rate_to_clk()