Searched refs:EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ (Results 1 – 1 of 1) sorted by relevance
65 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0) macro156 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ; in exynos4x12_rate_to_clk()