Searched refs:EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (Results 1 – 1 of 1) sorted by relevance
60 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0) macro141 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ; in exynos4x12_rate_to_clk()