Searched refs:EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG (Results 1 – 3 of 3) sorted by relevance
132 { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },173 EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
103 { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
446 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 macro