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Searched refs:EVERGREEN_CRTC3_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/radeon/
Devergreen_reg.h227 #define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) macro
Dradeon_display.c1508 EVERGREEN_CRTC3_REGISTER_OFFSET, in radeon_afmt_init()
1854 EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1856 EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
Dradeon_dp_mst.c19 EVERGREEN_CRTC3_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
Dcik.c6885 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7237 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7253 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7305 EVERGREEN_CRTC3_REGISTER_OFFSET); in cik_irq_ack()
7334 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7341 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7343 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
Dradeon_device.c679 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in radeon_card_posted()
Devergreen_cs.c1031 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1039 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
Datombios_crtc.c2252 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
Devergreen.c126 EVERGREEN_CRTC3_REGISTER_OFFSET,
Dsi.c146 EVERGREEN_CRTC3_REGISTER_OFFSET,