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Searched refs:DSPCNTR (Results 1 – 9 of 9) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/i915/display/ !
Di9xx_plane.c490 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_update_arm()
533 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_disable_arm()
555 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in g4x_primary_async_flip()
679 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
1002 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
Dintel_display.c3323 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_pipe_color_config()
9826 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); in i830_disable_pipe()
9828 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); in i830_disable_pipe()
9830 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); in i830_disable_pipe()
/linux-5.19.10/drivers/gpu/drm/i915/gvt/ !
Ddisplay.c189 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
500 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
Dfb_decoder.c214 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
Dcmd_parser.c1314 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1380 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
Dhandlers.c1014 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
/linux-5.19.10/drivers/gpu/drm/i915/ !
Dintel_gvt_mmio_table.c150 MMIO_D(DSPCNTR(PIPE_A)); in iterate_generic_mmio()
159 MMIO_D(DSPCNTR(PIPE_B)); in iterate_generic_mmio()
168 MMIO_D(DSPCNTR(PIPE_C)); in iterate_generic_mmio()
Dintel_pm.c7232 intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe), in g4x_disable_trickle_feed()
7233 intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
Di915_reg.h4392 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro