Searched refs:DPMTABLE_OD_UPDATE_SCLK (Results 1 – 13 of 13) sorted by relevance
189 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
1426 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()1534 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()3837 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()3873 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()3879 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
175 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
228 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
1023 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in smu7_check_dpm_table_updated()1050 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; in smu7_check_dpm_table_updated()1056 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()1664 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in smu7_update_avfs()4042 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in smu7_find_dpm_states_clocks_in_dpm_table()4156 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { in smu7_freeze_sclk_mclk_dpm()4198 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()4213 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()4312 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { in smu7_unfreeze_sclk_mclk_dpm()4684 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | in smu7_check_states_equal()
1629 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in vega10_populate_single_gfx_level()2537 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; in vega10_check_dpm_table_updated()2571 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in vega10_init_smc_table()3410 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in vega10_find_dpm_states_clocks_in_dpm_table()3446 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()3458 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()5531 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in vega10_odn_edit_dpm_table()
377 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
2205 (DPMTABLE_OD_UPDATE_SCLK + in vegam_program_mem_timing_parameters()
2255 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in fiji_program_mem_timing_parameters()
2168 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in iceland_program_mem_timing_parameters()
2139 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in polaris10_program_mem_timing_parameters()
2206 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in ci_program_mem_timing_parameters()
2557 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in tonga_program_mem_timing_parameters()