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Searched refs:DPIO_CH1 (Results 1 – 7 of 7) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c1164 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1165 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1166 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1167 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1168 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1169 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1170 MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1171 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1172 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
1173 MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1)); in iterate_bxt_mmio()
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/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_display_power_well.c1320 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1321 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1322 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1336 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) in assert_chv_phy_status()
1337 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1342 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) in assert_chv_phy_status()
1351 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && in assert_chv_phy_status()
1353 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1363 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) in assert_chv_phy_status()
1364 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); in assert_chv_phy_status()
[all …]
Dintel_dpio_phy.c171 [DPIO_CH1] = { .port = PORT_C },
258 port == phy_info->channel[DPIO_CH1].port) { in bxt_port_to_phy_channel()
260 *ch = DPIO_CH1; in bxt_port_to_phy_channel()
818 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable()
833 if (ch == DPIO_CH1) in chv_phy_pre_pll_enable()
841 if (ch == DPIO_CH1) in chv_phy_pre_pll_enable()
966 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
Dintel_display_types.h1734 return DPIO_CH1; in vlv_dig_port_to_channel()
1762 return DPIO_CH1; in vlv_pipe_to_channel()
Dintel_display_power.c1717 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | in chv_phy_control_init()
1746 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
1749 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); in chv_phy_control_init()
Dintel_display.h283 DPIO_CH1 enumerator
/linux-5.19.10/drivers/gpu/drm/i915/gvt/
Dhandlers.c550 ch = DPIO_CH1; in bxt_vgpu_get_dp_bitrate()
2763 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
2765 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()