Searched refs:DMA_CHAN_INTR_ENA (Results 1 – 3 of 3) sorted by relevance
91 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()98 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()103 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()110 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()115 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()122 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()127 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq()134 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq()141 u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_dma_interrupt()
124 ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_dma_init_channel()141 ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_dma_init_channel()200 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = in _dwmac4_dump_dma_regs()201 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); in _dwmac4_dump_dma_regs()
113 #define DMA_CHAN_INTR_ENA(x) (DMA_CHANX_BASE_ADDR(x) + 0x34) macro