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/linux-5.19.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
/linux-5.19.10/arch/arm/mach-omap2/
Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
Dsram243x.S52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
Dsram242x.S52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
/linux-5.19.10/arch/x86/boot/
Dearly_serial_console.c21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
109 dll = inb(port + DLL); in probe_baud()
/linux-5.19.10/tools/testing/kunit/
D.gitignore2 # Byte-compiled / optimized / DLL files
/linux-5.19.10/Documentation/devicetree/bindings/mmc/
Dsdhci-sprd.txt26 PHY DLL delays are used to delay the data valid window, and align the window
27 to sampling clock. PHY DLL delays can be configured by following properties,
Dcdns,sdhci.yaml33 # PHY DLL input delays:
83 # PHY DLL clock delays:
Dsdhci-st.txt27 to configure DLL inside the flashSS, if so reg-names must also be
32 for eMMC on stih407 family silicon to configure DLL inside FlashSS.
Dfsl-imx-esdhc.yaml94 This is used to set the clock delay for DLL(Delay Line) on override mode
97 chapter, DLL (Delay Line) section in RM for details.
Dsdhci-am654.yaml166 description: DLL trim select
172 description: DLL drive strength in ohms
/linux-5.19.10/arch/arm/mach-orion5x/
Dtsx09-common.c33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
Dterastation_pro2-setup.c276 writel(divisor & 0xff, UART1_REG(DLL)); in tsp2_power_off()
Dkurobox_pro-setup.c301 writel(divisor & 0xff, UART1_REG(DLL)); in kurobox_pro_power_off()
/linux-5.19.10/arch/x86/kernel/
Dearly_printk.c94 #define DLL 0 /* Divisor Latch Low */ macro
141 serial_out(early_serial_base, DLL, divisor & 0xff); in early_serial_hw_init()
/linux-5.19.10/drivers/usb/serial/
Dio_16654.h40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB macro
/linux-5.19.10/Documentation/misc-devices/
Doxsemi-tornado.rst94 and the clock divisor (DLM/DLL) as follows to obtain such rates if so
101 |0 0 0| CPR2:CPR | TCR | DLM:DLL |
112 For example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL
/linux-5.19.10/drivers/power/reset/
Dqnap-poweroff.c61 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_power_off()
/linux-5.19.10/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
110 Note: if DLL was bypassed, the odt will also stop working.
117 is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
118 Note: PHY DLL and PHY ODT are independent.
/linux-5.19.10/Documentation/virt/kvm/x86/
Derrata.rst32 Note however that any software (e.g ``WIN87EM.DLL``) expecting these features
/linux-5.19.10/drivers/net/hamradio/
Dbaycom_ser_fdx.c102 #define DLL(iobase) (iobase+0) macro
174 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
Dbaycom_ser_hdx.c88 #define DLL(iobase) (iobase+0) macro
159 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
Dyam.c159 #define DLL(iobase) (iobase+0) macro
295 outb(1, DLL(iobase)); in fpga_reset()
467 outb(divisor, DLL(dev->base_addr)); in yam_set_uart()

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