| /linux-5.19.10/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7723.c | 109 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
115 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
143 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
144 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
145 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
147 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
148 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
149 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
153 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
202 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7724.c | 148 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator
154 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
203 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
204 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
205 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
207 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
209 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
214 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
268 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7366.c | 105 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
112 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
142 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
143 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
144 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
191 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7343.c | 102 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
109 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
139 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
140 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
141 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
193 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7757.c | 60 enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; enumerator
72 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
110 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-shx3.c | 59 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; enumerator
70 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
111 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7785.c | 63 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, enumerator
77 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
129 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7786.c | 65 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator
76 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
136 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7722.c | 111 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
114 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
177 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7734.c | 67 enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR }; enumerator
73 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
184 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| /linux-5.19.10/arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7264.c | 74 enum { DIV4_I, DIV4_P, enumerator
82 [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
111 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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| D | clock-sh7269.c | 102 enum { DIV4_I, DIV4_B, enumerator
110 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
146 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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