Searched refs:DFL_PORT_BASE (Results 1 – 1 of 1) sorted by relevance
32 #define DFL_PORT_BASE 0x40 macro67 #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)86 #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1)115 #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)136 #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3)152 #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4)176 DFL_PORT_BASE + 5, __u32)187 DFL_PORT_BASE + 6, \199 DFL_PORT_BASE + 7, __u32)210 DFL_PORT_BASE + 8, \