1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_FDMA = 21, 21 TARGET_GCB = 27, 22 TARGET_ORG = 36, 23 TARGET_PTP = 41, 24 TARGET_QS = 42, 25 TARGET_QSYS = 46, 26 TARGET_REW = 47, 27 TARGET_SYS = 52, 28 NUM_TARGETS = 66 29 }; 30 31 #define __REG(...) __VA_ARGS__ 32 33 /* AFI:PORT_TBL:PORT_FRM_OUT */ 34 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 35 36 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 38 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 39 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 40 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 41 42 /* AFI:PORT_TBL:PORT_CFG */ 43 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 44 45 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 47 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 48 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 49 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 50 51 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 52 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 53 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 54 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 55 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 56 57 /* ANA:ANA:ADVLEARN */ 58 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 59 60 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 61 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 62 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 63 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 64 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 65 66 /* ANA:ANA:VLANMASK */ 67 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 68 69 /* ANA:ANA:ANAINTR */ 70 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 71 72 #define ANA_ANAINTR_INTR BIT(1) 73 #define ANA_ANAINTR_INTR_SET(x)\ 74 FIELD_PREP(ANA_ANAINTR_INTR, x) 75 #define ANA_ANAINTR_INTR_GET(x)\ 76 FIELD_GET(ANA_ANAINTR_INTR, x) 77 78 #define ANA_ANAINTR_INTR_ENA BIT(0) 79 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 80 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 81 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 82 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 83 84 /* ANA:ANA:AUTOAGE */ 85 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 86 87 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 88 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 89 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 90 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 91 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 92 93 /* ANA:ANA:FLOODING */ 94 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 95 96 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 97 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 98 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 99 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 100 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 101 102 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 103 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 104 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 105 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 106 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 107 108 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 109 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 110 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 111 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 112 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 113 114 /* ANA:ANA:FLOODING_IPMC */ 115 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 116 117 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 118 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 119 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 120 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 121 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 122 123 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 124 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 125 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 126 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 127 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 128 129 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 130 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 131 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 132 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 133 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 134 135 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 136 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 137 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 138 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 139 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 140 141 /* ANA:PGID:PGID */ 142 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 143 144 #define ANA_PGID_PGID GENMASK(8, 0) 145 #define ANA_PGID_PGID_SET(x)\ 146 FIELD_PREP(ANA_PGID_PGID, x) 147 #define ANA_PGID_PGID_GET(x)\ 148 FIELD_GET(ANA_PGID_PGID, x) 149 150 /* ANA:PGID:PGID_CFG */ 151 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 152 153 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 154 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 155 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 156 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 157 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 158 159 /* ANA:ANA_TABLES:MACHDATA */ 160 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 161 162 /* ANA:ANA_TABLES:MACLDATA */ 163 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 164 165 /* ANA:ANA_TABLES:MACACCESS */ 166 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 167 168 #define ANA_MACACCESS_CHANGE2SW BIT(17) 169 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 170 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 171 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 172 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 173 174 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 175 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 176 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 177 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 178 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 179 180 #define ANA_MACACCESS_VALID BIT(12) 181 #define ANA_MACACCESS_VALID_SET(x)\ 182 FIELD_PREP(ANA_MACACCESS_VALID, x) 183 #define ANA_MACACCESS_VALID_GET(x)\ 184 FIELD_GET(ANA_MACACCESS_VALID, x) 185 186 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 187 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 188 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 189 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 190 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 191 192 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 193 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 194 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 195 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 196 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 197 198 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 199 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 200 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 201 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 202 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 203 204 /* ANA:ANA_TABLES:MACTINDX */ 205 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 206 207 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 208 #define ANA_MACTINDX_BUCKET_SET(x)\ 209 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 210 #define ANA_MACTINDX_BUCKET_GET(x)\ 211 FIELD_GET(ANA_MACTINDX_BUCKET, x) 212 213 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 214 #define ANA_MACTINDX_M_INDEX_SET(x)\ 215 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 216 #define ANA_MACTINDX_M_INDEX_GET(x)\ 217 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 218 219 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 220 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 221 222 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 223 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 224 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 225 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 226 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 227 228 /* ANA:ANA_TABLES:VLANACCESS */ 229 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 230 231 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 232 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 233 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 234 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 235 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 236 237 /* ANA:ANA_TABLES:VLANTIDX */ 238 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 239 240 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 241 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 242 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 243 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 244 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 245 246 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 247 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 248 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 249 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 250 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 251 252 /* ANA:PORT:VLAN_CFG */ 253 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 254 255 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 256 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 257 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 258 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 259 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 260 261 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 262 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 263 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 264 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 265 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 266 267 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 268 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 269 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 270 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 271 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 272 273 /* ANA:PORT:DROP_CFG */ 274 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 275 276 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 277 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 278 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 279 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 280 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 281 282 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 283 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 284 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 285 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 286 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 287 288 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 289 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 290 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 291 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 292 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 293 294 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 295 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 296 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 297 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 298 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 299 300 /* ANA:PORT:CPU_FWD_CFG */ 301 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 302 303 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6) 304 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ 305 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 306 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ 307 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 308 309 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5) 310 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ 311 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 312 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ 313 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 314 315 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4) 316 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ 317 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 318 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ 319 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 320 321 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 322 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 323 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 324 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 325 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 326 327 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 328 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 329 330 /* ANA:PORT:PORT_CFG */ 331 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 332 333 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 334 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 335 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 336 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 337 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 338 339 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 340 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 341 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 342 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 343 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 344 345 #define ANA_PORT_CFG_RECV_ENA BIT(4) 346 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 347 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 348 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 349 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 350 351 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 352 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 353 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 354 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 355 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 356 357 /* ANA:PFC:PFC_CFG */ 358 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 359 360 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 361 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 362 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 363 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 364 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 365 366 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 367 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 368 369 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 370 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 371 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 372 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 373 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 374 375 /* DEV:PORT_MODE:CLOCK_CFG */ 376 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 377 378 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 379 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 380 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 381 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 382 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 383 384 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 385 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 386 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 387 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 388 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 389 390 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 391 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 392 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 393 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 394 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 395 396 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 397 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 398 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 399 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 400 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 401 402 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 403 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 404 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 405 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 406 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 407 408 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 409 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 410 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 411 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 412 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 413 414 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 415 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 416 417 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 418 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 419 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 420 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 421 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 422 423 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 424 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 425 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 426 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 427 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 428 429 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 430 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 431 432 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 433 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 434 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 435 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 436 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 437 438 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 439 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 440 441 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 442 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 443 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 444 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 445 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 446 447 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 448 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 449 450 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 451 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 452 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 453 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 454 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 455 456 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 457 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 458 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 459 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 460 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 461 462 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 463 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 464 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 465 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 466 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 467 468 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 469 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 470 471 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 472 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 473 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 474 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 475 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 476 477 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 478 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 479 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 480 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 481 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 482 483 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 484 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 485 486 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 487 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 488 489 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 490 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 491 492 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 493 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 494 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 495 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 496 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 497 498 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 499 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 500 501 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 502 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 503 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 504 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 505 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 506 507 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 508 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 509 510 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 511 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 512 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 513 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 514 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 515 516 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 517 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 518 519 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 520 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 521 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 522 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 523 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 524 525 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 526 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 527 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 528 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 529 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 530 531 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 532 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 533 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 534 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 535 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 536 537 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 538 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 539 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 540 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 541 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 542 543 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 544 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 545 546 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 547 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 548 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 549 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 550 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 551 552 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 553 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 554 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 555 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 556 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 557 558 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 559 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 560 561 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 562 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 563 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 564 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 565 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 566 567 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 568 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 569 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 570 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 571 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 572 573 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 574 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 575 576 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 577 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 578 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 579 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 580 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 581 582 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 583 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 584 585 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 586 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 587 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 588 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 589 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 590 591 /* FDMA:FDMA:FDMA_CH_RELOAD */ 592 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 593 594 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 595 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 596 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 597 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 598 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 599 600 /* FDMA:FDMA:FDMA_CH_DISABLE */ 601 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 602 603 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 604 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 605 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 606 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 607 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 608 609 /* FDMA:FDMA:FDMA_CH_DB_DISCARD */ 610 #define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4) 611 612 #define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0) 613 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\ 614 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 615 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\ 616 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 617 618 /* FDMA:FDMA:FDMA_DCB_LLP */ 619 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 620 621 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 622 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 623 624 /* FDMA:FDMA:FDMA_CH_ACTIVE */ 625 #define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4) 626 627 /* FDMA:FDMA:FDMA_CH_CFG */ 628 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 629 630 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4) 631 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 632 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 633 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 634 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 635 636 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3) 637 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 638 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 639 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 640 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 641 642 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1) 643 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 644 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 645 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 646 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 647 648 #define FDMA_CH_CFG_CH_MEM BIT(0) 649 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 650 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 651 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 652 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 653 654 /* FDMA:FDMA:FDMA_PORT_CTRL */ 655 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 656 657 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 658 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 659 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 660 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 661 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 662 663 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 664 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 665 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 666 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 667 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 668 669 /* FDMA:FDMA:FDMA_INTR_DB */ 670 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 671 672 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 673 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 674 675 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 676 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 677 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 678 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 679 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 680 681 /* FDMA:FDMA:FDMA_INTR_ERR */ 682 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 683 684 /* FDMA:FDMA:FDMA_ERRORS */ 685 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 686 687 /* PTP:PTP_CFG:PTP_PIN_INTR */ 688 #define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4) 689 690 #define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0) 691 #define PTP_PIN_INTR_INTR_PTP_SET(x)\ 692 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x) 693 #define PTP_PIN_INTR_INTR_PTP_GET(x)\ 694 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x) 695 696 /* PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 697 #define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4) 698 699 #define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0) 700 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\ 701 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x) 702 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\ 703 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x) 704 705 /* PTP:PTP_CFG:PTP_DOM_CFG */ 706 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4) 707 708 #define PTP_DOM_CFG_ENA GENMASK(11, 9) 709 #define PTP_DOM_CFG_ENA_SET(x)\ 710 FIELD_PREP(PTP_DOM_CFG_ENA, x) 711 #define PTP_DOM_CFG_ENA_GET(x)\ 712 FIELD_GET(PTP_DOM_CFG_ENA, x) 713 714 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0) 715 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ 716 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x) 717 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ 718 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x) 719 720 /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 721 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4) 722 723 /* PTP:PTP_PINS:PTP_PIN_CFG */ 724 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4) 725 726 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27) 727 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ 728 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x) 729 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ 730 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x) 731 732 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25) 733 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ 734 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x) 735 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ 736 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x) 737 738 #define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21) 739 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\ 740 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x) 741 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\ 742 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x) 743 744 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16) 745 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ 746 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x) 747 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ 748 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x) 749 750 /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 751 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4) 752 753 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0) 754 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ 755 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 756 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ 757 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 758 759 /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 760 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4) 761 762 /* PTP:PTP_PINS:PTP_TOD_NSEC */ 763 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4) 764 765 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0) 766 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ 767 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x) 768 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ 769 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x) 770 771 /* PTP:PTP_PINS:WF_HIGH_PERIOD */ 772 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 773 0, 1, 0, g, 8, 64, 24, 0, 1, 4) 774 775 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) 776 #define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0) 777 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) 778 779 /* PTP:PTP_PINS:WF_LOW_PERIOD */ 780 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 781 0, 1, 0, g, 8, 64, 28, 0, 1, 4) 782 783 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) 784 #define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0) 785 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0)) 786 787 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 788 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4) 789 790 #define PTP_TWOSTEP_CTRL_NXT BIT(11) 791 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ 792 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x) 793 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ 794 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x) 795 796 #define PTP_TWOSTEP_CTRL_VLD BIT(10) 797 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ 798 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x) 799 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ 800 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x) 801 802 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 803 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 804 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 805 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 806 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 807 808 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 809 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 810 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 811 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 812 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 813 814 #define PTP_TWOSTEP_CTRL_OVFL BIT(0) 815 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ 816 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x) 817 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ 818 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x) 819 820 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ 821 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4) 822 823 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2) 824 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 825 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 826 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 827 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 828 829 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 830 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 831 832 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 833 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 834 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 835 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 836 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 837 838 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 839 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 840 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 841 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 842 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 843 844 /* DEVCPU_QS:XTR:XTR_RD */ 845 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 846 847 /* DEVCPU_QS:XTR:XTR_FLUSH */ 848 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 849 850 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 851 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 852 853 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 854 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 855 856 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 857 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 858 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 859 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 860 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 861 862 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 863 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 864 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 865 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 866 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 867 868 /* DEVCPU_QS:INJ:INJ_WR */ 869 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 870 871 /* DEVCPU_QS:INJ:INJ_CTRL */ 872 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 873 874 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 875 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 876 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 877 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 878 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 879 880 #define QS_INJ_CTRL_EOF BIT(19) 881 #define QS_INJ_CTRL_EOF_SET(x)\ 882 FIELD_PREP(QS_INJ_CTRL_EOF, x) 883 #define QS_INJ_CTRL_EOF_GET(x)\ 884 FIELD_GET(QS_INJ_CTRL_EOF, x) 885 886 #define QS_INJ_CTRL_SOF BIT(18) 887 #define QS_INJ_CTRL_SOF_SET(x)\ 888 FIELD_PREP(QS_INJ_CTRL_SOF, x) 889 #define QS_INJ_CTRL_SOF_GET(x)\ 890 FIELD_GET(QS_INJ_CTRL_SOF, x) 891 892 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 893 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 894 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 895 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 896 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 897 898 /* DEVCPU_QS:INJ:INJ_STATUS */ 899 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 900 901 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 902 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 903 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 904 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 905 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 906 907 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 908 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 909 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 910 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 911 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 912 913 /* QSYS:SYSTEM:PORT_MODE */ 914 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 915 916 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 917 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 918 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 919 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 920 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 921 922 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 923 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 924 925 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 926 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 927 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 928 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 929 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 930 931 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 932 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 933 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 934 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 935 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 936 937 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 938 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 939 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 940 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 941 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 942 943 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 944 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 945 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 946 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 947 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 948 949 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 950 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 951 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 952 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 953 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 954 955 /* QSYS:SYSTEM:SW_STATUS */ 956 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 957 958 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 959 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 960 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 961 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 962 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 963 964 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 965 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 966 967 /* QSYS:RES_CTRL:RES_CFG */ 968 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 969 970 /* REW:PORT:PORT_VLAN_CFG */ 971 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 972 973 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 974 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 975 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 976 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 977 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 978 979 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 980 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 981 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 982 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 983 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 984 985 /* REW:PORT:TAG_CFG */ 986 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 987 988 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 989 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 990 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 991 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 992 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 993 994 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 995 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 996 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 997 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 998 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 999 1000 /* REW:PORT:PORT_CFG */ 1001 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 1002 1003 #define REW_PORT_CFG_NO_REWRITE BIT(0) 1004 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 1005 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 1006 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 1007 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 1008 1009 /* SYS:SYSTEM:RESET_CFG */ 1010 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 1011 1012 #define SYS_RESET_CFG_CORE_ENA BIT(0) 1013 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 1014 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 1015 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 1016 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 1017 1018 /* SYS:SYSTEM:PORT_MODE */ 1019 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 1020 1021 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 1022 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 1023 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 1024 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 1025 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 1026 1027 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 1028 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 1029 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 1030 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 1031 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 1032 1033 /* SYS:SYSTEM:FRONT_PORT_MODE */ 1034 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 1035 1036 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 1037 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 1038 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1039 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 1040 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1041 1042 /* SYS:SYSTEM:FRM_AGING */ 1043 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 1044 1045 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 1046 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 1047 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 1048 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 1049 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 1050 1051 /* SYS:SYSTEM:STAT_CFG */ 1052 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 1053 1054 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 1055 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 1056 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 1057 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 1058 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 1059 1060 /* SYS:PAUSE_CFG:PAUSE_CFG */ 1061 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 1062 1063 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 1064 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 1065 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 1066 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 1067 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 1068 1069 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 1070 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 1071 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 1072 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 1073 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 1074 1075 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 1076 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 1077 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 1078 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 1079 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 1080 1081 /* SYS:PAUSE_CFG:ATOP */ 1082 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 1083 1084 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 1085 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 1086 1087 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 1088 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 1089 1090 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 1091 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 1092 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1093 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 1094 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1095 1096 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 1097 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 1098 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1099 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 1100 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1101 1102 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 1103 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 1104 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1105 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 1106 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1107 1108 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 1109 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 1110 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1111 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 1112 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1113 1114 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 1115 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 1116 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1117 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 1118 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1119 1120 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 1121 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 1122 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1123 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 1124 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1125 1126 /* SYS:STAT:CNT */ 1127 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 1128 1129 /* SYS:RAM_CTRL:RAM_INIT */ 1130 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 1131 1132 #define SYS_RAM_INIT_RAM_INIT BIT(1) 1133 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 1134 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 1135 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 1136 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 1137 1138 #endif /* _LAN966X_REGS_H_ */ 1139