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Searched refs:CSR_BASE (Results 1 – 5 of 5) sorted by relevance

/linux-5.19.10/drivers/net/wireless/intel/iwlegacy/
Dcsr.h83 #define CSR_BASE (0x000) macro
85 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
87 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
88 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
89 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */
90 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
91 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */
92 #define CSR_GP_CNTRL (CSR_BASE+0x024)
95 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
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/linux-5.19.10/drivers/net/wireless/intel/iwlwifi/
Diwl-csr.h27 #define CSR_BASE (0x000) macro
29 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
31 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
32 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
33 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
34 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
35 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
36 #define CSR_GP_CNTRL (CSR_BASE+0x024)
37 #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
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/linux-5.19.10/arch/sparc/include/asm/
Dobio.h27 #define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT) macro
127 "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT), in bw_get_prof_limit()
136 "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT), in bw_set_prof_limit()
146 "r" (CSR_BASE(cpu) + BW_CTRL), in bw_get_ctrl()
155 "r" (CSR_BASE(cpu) + BW_CTRL), in bw_set_ctrl()
/linux-5.19.10/drivers/scsi/
Dg_NCR5380.c385 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); in generic_NCR5380_init_one()
507 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); in wait_for_53c80_access()
525 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE | CSR_TRANS_DIR); in generic_NCR5380_precv()
561 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); in generic_NCR5380_precv()
592 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); in generic_NCR5380_psend()
640 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); in generic_NCR5380_psend()
DNCR5380.h170 #define CSR_BASE CSR_53C80_INTR macro