1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) ST-Ericsson SA 2010
4  * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
5  * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
6  * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
7  * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
8  * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
9  */
10 
11 #ifndef _CRYP_P_H_
12 #define _CRYP_P_H_
13 
14 #include <linux/io.h>
15 #include <linux/bitops.h>
16 
17 #include "cryp.h"
18 #include "cryp_irqp.h"
19 
20 /*
21  * Generic Macros
22  */
23 #define CRYP_SET_BITS(reg_name, mask) \
24 	writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
25 
26 #define CRYP_WRITE_BIT(reg_name, val, mask) \
27 	writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
28 			((val) & (mask))), reg_name)
29 
30 #define CRYP_TEST_BITS(reg_name, val) \
31 	(readl_relaxed(reg_name) & (val))
32 
33 #define CRYP_PUT_BITS(reg, val, shift, mask) \
34 	writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
35 		(((u32)val << shift) & (mask))), reg)
36 
37 /*
38  * CRYP specific Macros
39  */
40 #define CRYP_PERIPHERAL_ID0		0xE3
41 #define CRYP_PERIPHERAL_ID1		0x05
42 
43 #define CRYP_PERIPHERAL_ID2_DB8500	0x28
44 #define CRYP_PERIPHERAL_ID3		0x00
45 
46 #define CRYP_PCELL_ID0			0x0D
47 #define CRYP_PCELL_ID1			0xF0
48 #define CRYP_PCELL_ID2			0x05
49 #define CRYP_PCELL_ID3			0xB1
50 
51 /*
52  * CRYP register default values
53  */
54 #define MAX_DEVICE_SUPPORT		2
55 
56 /* Priv set, keyrden set and datatype 8bits swapped set as default. */
57 #define CRYP_CR_DEFAULT			0x0482
58 #define CRYP_DMACR_DEFAULT		0x0
59 #define CRYP_IMSC_DEFAULT		0x0
60 #define CRYP_DIN_DEFAULT		0x0
61 #define CRYP_DOUT_DEFAULT		0x0
62 #define CRYP_KEY_DEFAULT		0x0
63 #define CRYP_INIT_VECT_DEFAULT		0x0
64 
65 /*
66  * CRYP Control register specific mask
67  */
68 #define CRYP_CR_SECURE_MASK		BIT(0)
69 #define CRYP_CR_PRLG_MASK		BIT(1)
70 #define CRYP_CR_ALGODIR_MASK		BIT(2)
71 #define CRYP_CR_ALGOMODE_MASK		(BIT(5) | BIT(4) | BIT(3))
72 #define CRYP_CR_DATATYPE_MASK		(BIT(7) | BIT(6))
73 #define CRYP_CR_KEYSIZE_MASK		(BIT(9) | BIT(8))
74 #define CRYP_CR_KEYRDEN_MASK		BIT(10)
75 #define CRYP_CR_KSE_MASK		BIT(11)
76 #define CRYP_CR_START_MASK		BIT(12)
77 #define CRYP_CR_INIT_MASK		BIT(13)
78 #define CRYP_CR_FFLUSH_MASK		BIT(14)
79 #define CRYP_CR_CRYPEN_MASK		BIT(15)
80 #define CRYP_CR_CONTEXT_SAVE_MASK	(CRYP_CR_SECURE_MASK |\
81 					 CRYP_CR_PRLG_MASK |\
82 					 CRYP_CR_ALGODIR_MASK |\
83 					 CRYP_CR_ALGOMODE_MASK |\
84 					 CRYP_CR_KEYSIZE_MASK |\
85 					 CRYP_CR_KEYRDEN_MASK |\
86 					 CRYP_CR_DATATYPE_MASK)
87 
88 
89 #define CRYP_SR_INFIFO_READY_MASK	(BIT(0) | BIT(1))
90 #define CRYP_SR_IFEM_MASK		BIT(0)
91 #define CRYP_SR_BUSY_MASK		BIT(4)
92 
93 /*
94  * Bit position used while setting bits in register
95  */
96 #define CRYP_CR_PRLG_POS		1
97 #define CRYP_CR_ALGODIR_POS		2
98 #define CRYP_CR_ALGOMODE_POS		3
99 #define CRYP_CR_DATATYPE_POS		6
100 #define CRYP_CR_KEYSIZE_POS		8
101 #define CRYP_CR_KEYRDEN_POS		10
102 #define CRYP_CR_KSE_POS			11
103 #define CRYP_CR_START_POS		12
104 #define CRYP_CR_INIT_POS		13
105 #define CRYP_CR_CRYPEN_POS		15
106 
107 #define CRYP_SR_BUSY_POS		4
108 
109 /*
110  * CRYP PCRs------PC_NAND control register
111  * BIT_MASK
112  */
113 #define CRYP_DMA_REQ_MASK		(BIT(1) | BIT(0))
114 #define CRYP_DMA_REQ_MASK_POS		0
115 
116 
117 struct cryp_system_context {
118 	/* CRYP Register structure */
119 	struct cryp_register *p_cryp_reg[MAX_DEVICE_SUPPORT];
120 };
121 
122 #endif
123