1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-01-30 18:25:22)
12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2020-12-31 19:26:32)
13 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-06-21 15:24:24)
14 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14609 bytes, from 2021-11-24 23:05:10)
15 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  69086 bytes, from 2022-03-03 16:41:33)
16 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2021-11-24 23:05:10)
17 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113358 bytes, from 2022-01-31 23:06:21)
18 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149512 bytes, from 2022-01-31 23:06:21)
19 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 184954 bytes, from 2022-03-03 16:41:33)
20 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-07-22 15:21:56)
21 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-01-30 18:25:22)
22 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-07-22 15:21:56)
23 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-07-22 15:21:56)
24 
25 Copyright (C) 2013-2022 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28 
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36 
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40 
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49 
50 
51 enum vgt_event_type {
52 	VS_DEALLOC = 0,
53 	PS_DEALLOC = 1,
54 	VS_DONE_TS = 2,
55 	PS_DONE_TS = 3,
56 	CACHE_FLUSH_TS = 4,
57 	CONTEXT_DONE = 5,
58 	CACHE_FLUSH = 6,
59 	VIZQUERY_START = 7,
60 	HLSQ_FLUSH = 7,
61 	VIZQUERY_END = 8,
62 	SC_WAIT_WC = 9,
63 	WRITE_PRIMITIVE_COUNTS = 9,
64 	START_PRIMITIVE_CTRS = 11,
65 	STOP_PRIMITIVE_CTRS = 12,
66 	RST_PIX_CNT = 13,
67 	RST_VTX_CNT = 14,
68 	TILE_FLUSH = 15,
69 	STAT_EVENT = 16,
70 	CACHE_FLUSH_AND_INV_TS_EVENT = 20,
71 	ZPASS_DONE = 21,
72 	CACHE_FLUSH_AND_INV_EVENT = 22,
73 	RB_DONE_TS = 22,
74 	PERFCOUNTER_START = 23,
75 	PERFCOUNTER_STOP = 24,
76 	VS_FETCH_DONE = 27,
77 	FACENESS_FLUSH = 28,
78 	WT_DONE_TS = 8,
79 	FLUSH_SO_0 = 17,
80 	FLUSH_SO_1 = 18,
81 	FLUSH_SO_2 = 19,
82 	FLUSH_SO_3 = 20,
83 	PC_CCU_INVALIDATE_DEPTH = 24,
84 	PC_CCU_INVALIDATE_COLOR = 25,
85 	PC_CCU_RESOLVE_TS = 26,
86 	PC_CCU_FLUSH_DEPTH_TS = 28,
87 	PC_CCU_FLUSH_COLOR_TS = 29,
88 	BLIT = 30,
89 	UNK_25 = 37,
90 	LRZ_FLUSH = 38,
91 	BLIT_OP_FILL_2D = 39,
92 	BLIT_OP_COPY_2D = 40,
93 	BLIT_OP_SCALE_2D = 42,
94 	CONTEXT_DONE_2D = 43,
95 	UNK_2C = 44,
96 	UNK_2D = 45,
97 	CACHE_INVALIDATE = 49,
98 };
99 
100 enum pc_di_primtype {
101 	DI_PT_NONE = 0,
102 	DI_PT_POINTLIST_PSIZE = 1,
103 	DI_PT_LINELIST = 2,
104 	DI_PT_LINESTRIP = 3,
105 	DI_PT_TRILIST = 4,
106 	DI_PT_TRIFAN = 5,
107 	DI_PT_TRISTRIP = 6,
108 	DI_PT_LINELOOP = 7,
109 	DI_PT_RECTLIST = 8,
110 	DI_PT_POINTLIST = 9,
111 	DI_PT_LINE_ADJ = 10,
112 	DI_PT_LINESTRIP_ADJ = 11,
113 	DI_PT_TRI_ADJ = 12,
114 	DI_PT_TRISTRIP_ADJ = 13,
115 	DI_PT_PATCHES0 = 31,
116 	DI_PT_PATCHES1 = 32,
117 	DI_PT_PATCHES2 = 33,
118 	DI_PT_PATCHES3 = 34,
119 	DI_PT_PATCHES4 = 35,
120 	DI_PT_PATCHES5 = 36,
121 	DI_PT_PATCHES6 = 37,
122 	DI_PT_PATCHES7 = 38,
123 	DI_PT_PATCHES8 = 39,
124 	DI_PT_PATCHES9 = 40,
125 	DI_PT_PATCHES10 = 41,
126 	DI_PT_PATCHES11 = 42,
127 	DI_PT_PATCHES12 = 43,
128 	DI_PT_PATCHES13 = 44,
129 	DI_PT_PATCHES14 = 45,
130 	DI_PT_PATCHES15 = 46,
131 	DI_PT_PATCHES16 = 47,
132 	DI_PT_PATCHES17 = 48,
133 	DI_PT_PATCHES18 = 49,
134 	DI_PT_PATCHES19 = 50,
135 	DI_PT_PATCHES20 = 51,
136 	DI_PT_PATCHES21 = 52,
137 	DI_PT_PATCHES22 = 53,
138 	DI_PT_PATCHES23 = 54,
139 	DI_PT_PATCHES24 = 55,
140 	DI_PT_PATCHES25 = 56,
141 	DI_PT_PATCHES26 = 57,
142 	DI_PT_PATCHES27 = 58,
143 	DI_PT_PATCHES28 = 59,
144 	DI_PT_PATCHES29 = 60,
145 	DI_PT_PATCHES30 = 61,
146 	DI_PT_PATCHES31 = 62,
147 };
148 
149 enum pc_di_src_sel {
150 	DI_SRC_SEL_DMA = 0,
151 	DI_SRC_SEL_IMMEDIATE = 1,
152 	DI_SRC_SEL_AUTO_INDEX = 2,
153 	DI_SRC_SEL_AUTO_XFB = 3,
154 };
155 
156 enum pc_di_face_cull_sel {
157 	DI_FACE_CULL_NONE = 0,
158 	DI_FACE_CULL_FETCH = 1,
159 	DI_FACE_BACKFACE_CULL = 2,
160 	DI_FACE_FRONTFACE_CULL = 3,
161 };
162 
163 enum pc_di_index_size {
164 	INDEX_SIZE_IGN = 0,
165 	INDEX_SIZE_16_BIT = 0,
166 	INDEX_SIZE_32_BIT = 1,
167 	INDEX_SIZE_8_BIT = 2,
168 	INDEX_SIZE_INVALID = 0,
169 };
170 
171 enum pc_di_vis_cull_mode {
172 	IGNORE_VISIBILITY = 0,
173 	USE_VISIBILITY = 1,
174 };
175 
176 enum adreno_pm4_packet_type {
177 	CP_TYPE0_PKT = 0,
178 	CP_TYPE1_PKT = 0x40000000,
179 	CP_TYPE2_PKT = 0x80000000,
180 	CP_TYPE3_PKT = 0xc0000000,
181 	CP_TYPE4_PKT = 0x40000000,
182 	CP_TYPE7_PKT = 0x70000000,
183 };
184 
185 enum adreno_pm4_type3_packets {
186 	CP_ME_INIT = 72,
187 	CP_NOP = 16,
188 	CP_PREEMPT_ENABLE = 28,
189 	CP_PREEMPT_TOKEN = 30,
190 	CP_INDIRECT_BUFFER = 63,
191 	CP_INDIRECT_BUFFER_CHAIN = 87,
192 	CP_INDIRECT_BUFFER_PFD = 55,
193 	CP_WAIT_FOR_IDLE = 38,
194 	CP_WAIT_REG_MEM = 60,
195 	CP_WAIT_REG_EQ = 82,
196 	CP_WAIT_REG_GTE = 83,
197 	CP_WAIT_UNTIL_READ = 92,
198 	CP_WAIT_IB_PFD_COMPLETE = 93,
199 	CP_REG_RMW = 33,
200 	CP_SET_BIN_DATA = 47,
201 	CP_SET_BIN_DATA5 = 47,
202 	CP_REG_TO_MEM = 62,
203 	CP_MEM_WRITE = 61,
204 	CP_MEM_WRITE_CNTR = 79,
205 	CP_COND_EXEC = 68,
206 	CP_COND_WRITE = 69,
207 	CP_COND_WRITE5 = 69,
208 	CP_EVENT_WRITE = 70,
209 	CP_EVENT_WRITE_SHD = 88,
210 	CP_EVENT_WRITE_CFL = 89,
211 	CP_EVENT_WRITE_ZPD = 91,
212 	CP_RUN_OPENCL = 49,
213 	CP_DRAW_INDX = 34,
214 	CP_DRAW_INDX_2 = 54,
215 	CP_DRAW_INDX_BIN = 52,
216 	CP_DRAW_INDX_2_BIN = 53,
217 	CP_VIZ_QUERY = 35,
218 	CP_SET_STATE = 37,
219 	CP_SET_CONSTANT = 45,
220 	CP_IM_LOAD = 39,
221 	CP_IM_LOAD_IMMEDIATE = 43,
222 	CP_LOAD_CONSTANT_CONTEXT = 46,
223 	CP_INVALIDATE_STATE = 59,
224 	CP_SET_SHADER_BASES = 74,
225 	CP_SET_BIN_MASK = 80,
226 	CP_SET_BIN_SELECT = 81,
227 	CP_CONTEXT_UPDATE = 94,
228 	CP_INTERRUPT = 64,
229 	CP_IM_STORE = 44,
230 	CP_SET_DRAW_INIT_FLAGS = 75,
231 	CP_SET_PROTECTED_MODE = 95,
232 	CP_BOOTSTRAP_UCODE = 111,
233 	CP_LOAD_STATE = 48,
234 	CP_LOAD_STATE4 = 48,
235 	CP_COND_INDIRECT_BUFFER_PFE = 58,
236 	CP_COND_INDIRECT_BUFFER_PFD = 50,
237 	CP_INDIRECT_BUFFER_PFE = 63,
238 	CP_SET_BIN = 76,
239 	CP_TEST_TWO_MEMS = 113,
240 	CP_REG_WR_NO_CTXT = 120,
241 	CP_RECORD_PFP_TIMESTAMP = 17,
242 	CP_SET_SECURE_MODE = 102,
243 	CP_WAIT_FOR_ME = 19,
244 	CP_SET_DRAW_STATE = 67,
245 	CP_DRAW_INDX_OFFSET = 56,
246 	CP_DRAW_INDIRECT = 40,
247 	CP_DRAW_INDX_INDIRECT = 41,
248 	CP_DRAW_INDIRECT_MULTI = 42,
249 	CP_DRAW_AUTO = 36,
250 	CP_DRAW_PRED_ENABLE_GLOBAL = 25,
251 	CP_DRAW_PRED_ENABLE_LOCAL = 26,
252 	CP_DRAW_PRED_SET = 78,
253 	CP_WIDE_REG_WRITE = 116,
254 	CP_SCRATCH_TO_REG = 77,
255 	CP_REG_TO_SCRATCH = 74,
256 	CP_WAIT_MEM_WRITES = 18,
257 	CP_COND_REG_EXEC = 71,
258 	CP_MEM_TO_REG = 66,
259 	CP_EXEC_CS_INDIRECT = 65,
260 	CP_EXEC_CS = 51,
261 	CP_PERFCOUNTER_ACTION = 80,
262 	CP_SMMU_TABLE_UPDATE = 83,
263 	CP_SET_MARKER = 101,
264 	CP_SET_PSEUDO_REG = 86,
265 	CP_CONTEXT_REG_BUNCH = 92,
266 	CP_YIELD_ENABLE = 28,
267 	CP_SKIP_IB2_ENABLE_GLOBAL = 29,
268 	CP_SKIP_IB2_ENABLE_LOCAL = 35,
269 	CP_SET_SUBDRAW_SIZE = 53,
270 	CP_WHERE_AM_I = 98,
271 	CP_SET_VISIBILITY_OVERRIDE = 100,
272 	CP_PREEMPT_ENABLE_GLOBAL = 105,
273 	CP_PREEMPT_ENABLE_LOCAL = 106,
274 	CP_CONTEXT_SWITCH_YIELD = 107,
275 	CP_SET_RENDER_MODE = 108,
276 	CP_COMPUTE_CHECKPOINT = 110,
277 	CP_MEM_TO_MEM = 115,
278 	CP_BLIT = 44,
279 	CP_REG_TEST = 57,
280 	CP_SET_MODE = 99,
281 	CP_LOAD_STATE6_GEOM = 50,
282 	CP_LOAD_STATE6_FRAG = 52,
283 	CP_LOAD_STATE6 = 54,
284 	IN_IB_PREFETCH_END = 23,
285 	IN_SUBBLK_PREFETCH = 31,
286 	IN_INSTR_PREFETCH = 32,
287 	IN_INSTR_MATCH = 71,
288 	IN_CONST_PREFETCH = 73,
289 	IN_INCR_UPDT_STATE = 85,
290 	IN_INCR_UPDT_CONST = 86,
291 	IN_INCR_UPDT_INSTR = 87,
292 	PKT4 = 4,
293 	CP_SCRATCH_WRITE = 76,
294 	CP_REG_TO_MEM_OFFSET_MEM = 116,
295 	CP_REG_TO_MEM_OFFSET_REG = 114,
296 	CP_WAIT_MEM_GTE = 20,
297 	CP_WAIT_TWO_REGS = 112,
298 	CP_MEMCPY = 117,
299 	CP_SET_BIN_DATA5_OFFSET = 46,
300 	CP_SET_CTXSWITCH_IB = 85,
301 	CP_REG_WRITE = 109,
302 	CP_START_BIN = 80,
303 	CP_END_BIN = 81,
304 };
305 
306 enum adreno_state_block {
307 	SB_VERT_TEX = 0,
308 	SB_VERT_MIPADDR = 1,
309 	SB_FRAG_TEX = 2,
310 	SB_FRAG_MIPADDR = 3,
311 	SB_VERT_SHADER = 4,
312 	SB_GEOM_SHADER = 5,
313 	SB_FRAG_SHADER = 6,
314 	SB_COMPUTE_SHADER = 7,
315 };
316 
317 enum adreno_state_type {
318 	ST_SHADER = 0,
319 	ST_CONSTANTS = 1,
320 };
321 
322 enum adreno_state_src {
323 	SS_DIRECT = 0,
324 	SS_INVALID_ALL_IC = 2,
325 	SS_INVALID_PART_IC = 3,
326 	SS_INDIRECT = 4,
327 	SS_INDIRECT_TCM = 5,
328 	SS_INDIRECT_STM = 6,
329 };
330 
331 enum a4xx_state_block {
332 	SB4_VS_TEX = 0,
333 	SB4_HS_TEX = 1,
334 	SB4_DS_TEX = 2,
335 	SB4_GS_TEX = 3,
336 	SB4_FS_TEX = 4,
337 	SB4_CS_TEX = 5,
338 	SB4_VS_SHADER = 8,
339 	SB4_HS_SHADER = 9,
340 	SB4_DS_SHADER = 10,
341 	SB4_GS_SHADER = 11,
342 	SB4_FS_SHADER = 12,
343 	SB4_CS_SHADER = 13,
344 	SB4_SSBO = 14,
345 	SB4_CS_SSBO = 15,
346 };
347 
348 enum a4xx_state_type {
349 	ST4_SHADER = 0,
350 	ST4_CONSTANTS = 1,
351 	ST4_UBO = 2,
352 };
353 
354 enum a4xx_state_src {
355 	SS4_DIRECT = 0,
356 	SS4_INDIRECT = 2,
357 };
358 
359 enum a6xx_state_block {
360 	SB6_VS_TEX = 0,
361 	SB6_HS_TEX = 1,
362 	SB6_DS_TEX = 2,
363 	SB6_GS_TEX = 3,
364 	SB6_FS_TEX = 4,
365 	SB6_CS_TEX = 5,
366 	SB6_VS_SHADER = 8,
367 	SB6_HS_SHADER = 9,
368 	SB6_DS_SHADER = 10,
369 	SB6_GS_SHADER = 11,
370 	SB6_FS_SHADER = 12,
371 	SB6_CS_SHADER = 13,
372 	SB6_IBO = 14,
373 	SB6_CS_IBO = 15,
374 };
375 
376 enum a6xx_state_type {
377 	ST6_SHADER = 0,
378 	ST6_CONSTANTS = 1,
379 	ST6_UBO = 2,
380 	ST6_IBO = 3,
381 };
382 
383 enum a6xx_state_src {
384 	SS6_DIRECT = 0,
385 	SS6_BINDLESS = 1,
386 	SS6_INDIRECT = 2,
387 	SS6_UBO = 3,
388 };
389 
390 enum a4xx_index_size {
391 	INDEX4_SIZE_8_BIT = 0,
392 	INDEX4_SIZE_16_BIT = 1,
393 	INDEX4_SIZE_32_BIT = 2,
394 };
395 
396 enum a6xx_patch_type {
397 	TESS_QUADS = 0,
398 	TESS_TRIANGLES = 1,
399 	TESS_ISOLINES = 2,
400 };
401 
402 enum a6xx_draw_indirect_opcode {
403 	INDIRECT_OP_NORMAL = 2,
404 	INDIRECT_OP_INDEXED = 4,
405 	INDIRECT_OP_INDIRECT_COUNT = 6,
406 	INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
407 };
408 
409 enum cp_draw_pred_src {
410 	PRED_SRC_MEM = 5,
411 };
412 
413 enum cp_draw_pred_test {
414 	NE_0_PASS = 0,
415 	EQ_0_PASS = 1,
416 };
417 
418 enum cp_cond_function {
419 	WRITE_ALWAYS = 0,
420 	WRITE_LT = 1,
421 	WRITE_LE = 2,
422 	WRITE_EQ = 3,
423 	WRITE_NE = 4,
424 	WRITE_GE = 5,
425 	WRITE_GT = 6,
426 };
427 
428 enum render_mode_cmd {
429 	BYPASS = 1,
430 	BINNING = 2,
431 	GMEM = 3,
432 	BLIT2D = 5,
433 	BLIT2DSCALE = 7,
434 	END2D = 8,
435 };
436 
437 enum cp_blit_cmd {
438 	BLIT_OP_FILL = 0,
439 	BLIT_OP_COPY = 1,
440 	BLIT_OP_SCALE = 3,
441 };
442 
443 enum a6xx_marker {
444 	RM6_BYPASS = 1,
445 	RM6_BINNING = 2,
446 	RM6_GMEM = 4,
447 	RM6_ENDVIS = 5,
448 	RM6_RESOLVE = 6,
449 	RM6_YIELD = 7,
450 	RM6_COMPUTE = 8,
451 	RM6_BLIT2DSCALE = 12,
452 	RM6_IB1LIST_START = 13,
453 	RM6_IB1LIST_END = 14,
454 	RM6_IFPC_ENABLE = 256,
455 	RM6_IFPC_DISABLE = 257,
456 };
457 
458 enum pseudo_reg {
459 	SMMU_INFO = 0,
460 	NON_SECURE_SAVE_ADDR = 1,
461 	SECURE_SAVE_ADDR = 2,
462 	NON_PRIV_SAVE_ADDR = 3,
463 	COUNTER = 4,
464 };
465 
466 enum compare_mode {
467 	PRED_TEST = 1,
468 	REG_COMPARE = 2,
469 	RENDER_MODE = 3,
470 };
471 
472 enum ctxswitch_ib {
473 	RESTORE_IB = 0,
474 	YIELD_RESTORE_IB = 1,
475 	SAVE_IB = 2,
476 	RB_SAVE_IB = 3,
477 };
478 
479 enum reg_tracker {
480 	TRACK_CNTL_REG = 1,
481 	TRACK_RENDER_CNTL = 2,
482 	UNK_EVENT_WRITE = 4,
483 };
484 
485 #define REG_CP_LOAD_STATE_0					0x00000000
486 #define CP_LOAD_STATE_0_DST_OFF__MASK				0x0000ffff
487 #define CP_LOAD_STATE_0_DST_OFF__SHIFT				0
CP_LOAD_STATE_0_DST_OFF(uint32_t val)488 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
489 {
490 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
491 }
492 #define CP_LOAD_STATE_0_STATE_SRC__MASK				0x00070000
493 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT			16
CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)494 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
495 {
496 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
497 }
498 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK			0x00380000
499 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT			19
CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)500 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
501 {
502 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
503 }
504 #define CP_LOAD_STATE_0_NUM_UNIT__MASK				0xffc00000
505 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT				22
CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)506 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
507 {
508 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
509 }
510 
511 #define REG_CP_LOAD_STATE_1					0x00000001
512 #define CP_LOAD_STATE_1_STATE_TYPE__MASK			0x00000003
513 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT			0
CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)514 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
515 {
516 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
517 }
518 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK			0xfffffffc
519 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT			2
CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)520 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
521 {
522 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
523 }
524 
525 #define REG_CP_LOAD_STATE4_0					0x00000000
526 #define CP_LOAD_STATE4_0_DST_OFF__MASK				0x00003fff
527 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT				0
CP_LOAD_STATE4_0_DST_OFF(uint32_t val)528 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
529 {
530 	return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
531 }
532 #define CP_LOAD_STATE4_0_STATE_SRC__MASK			0x00030000
533 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT			16
CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)534 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
535 {
536 	return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
537 }
538 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK			0x003c0000
539 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT			18
CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)540 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
541 {
542 	return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
543 }
544 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK				0xffc00000
545 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT			22
CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)546 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
547 {
548 	return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
549 }
550 
551 #define REG_CP_LOAD_STATE4_1					0x00000001
552 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK			0x00000003
553 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT			0
CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)554 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
555 {
556 	return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
557 }
558 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK			0xfffffffc
559 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT			2
CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)560 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
561 {
562 	return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
563 }
564 
565 #define REG_CP_LOAD_STATE4_2					0x00000002
566 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK			0xffffffff
567 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT			0
CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)568 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
569 {
570 	return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
571 }
572 
573 #define REG_CP_LOAD_STATE6_0					0x00000000
574 #define CP_LOAD_STATE6_0_DST_OFF__MASK				0x00003fff
575 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT				0
CP_LOAD_STATE6_0_DST_OFF(uint32_t val)576 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
577 {
578 	return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
579 }
580 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK			0x0000c000
581 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT			14
CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)582 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
583 {
584 	return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
585 }
586 #define CP_LOAD_STATE6_0_STATE_SRC__MASK			0x00030000
587 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT			16
CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)588 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
589 {
590 	return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
591 }
592 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK			0x003c0000
593 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT			18
CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)594 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
595 {
596 	return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
597 }
598 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK				0xffc00000
599 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT			22
CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)600 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
601 {
602 	return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
603 }
604 
605 #define REG_CP_LOAD_STATE6_1					0x00000001
606 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK			0xfffffffc
607 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT			2
CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)608 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
609 {
610 	return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
611 }
612 
613 #define REG_CP_LOAD_STATE6_2					0x00000002
614 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK			0xffffffff
615 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT			0
CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)616 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
617 {
618 	return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
619 }
620 
621 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR				0x00000001
622 
623 #define REG_CP_DRAW_INDX_0					0x00000000
624 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK				0xffffffff
625 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT				0
CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)626 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
627 {
628 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
629 }
630 
631 #define REG_CP_DRAW_INDX_1					0x00000001
632 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK				0x0000003f
633 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT				0
CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)634 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
635 {
636 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
637 }
638 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK			0x000000c0
639 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT			6
CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)640 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
641 {
642 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
643 }
644 #define CP_DRAW_INDX_1_VIS_CULL__MASK				0x00000600
645 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT				9
CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)646 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
647 {
648 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
649 }
650 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK				0x00000800
651 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT			11
CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)652 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
653 {
654 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
655 }
656 #define CP_DRAW_INDX_1_NOT_EOP					0x00001000
657 #define CP_DRAW_INDX_1_SMALL_INDEX				0x00002000
658 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
659 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK			0xff000000
660 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT			24
CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)661 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
662 {
663 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
664 }
665 
666 #define REG_CP_DRAW_INDX_2					0x00000002
667 #define CP_DRAW_INDX_2_NUM_INDICES__MASK			0xffffffff
668 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT			0
CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)669 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
670 {
671 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
672 }
673 
674 #define REG_CP_DRAW_INDX_3					0x00000003
675 #define CP_DRAW_INDX_3_INDX_BASE__MASK				0xffffffff
676 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT				0
CP_DRAW_INDX_3_INDX_BASE(uint32_t val)677 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
678 {
679 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
680 }
681 
682 #define REG_CP_DRAW_INDX_4					0x00000004
683 #define CP_DRAW_INDX_4_INDX_SIZE__MASK				0xffffffff
684 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT				0
CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)685 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
686 {
687 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
688 }
689 
690 #define REG_CP_DRAW_INDX_2_0					0x00000000
691 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK			0xffffffff
692 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT			0
CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)693 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
694 {
695 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
696 }
697 
698 #define REG_CP_DRAW_INDX_2_1					0x00000001
699 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK			0x0000003f
700 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT			0
CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)701 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
702 {
703 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
704 }
705 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK			0x000000c0
706 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT			6
CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)707 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
708 {
709 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
710 }
711 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK				0x00000600
712 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT			9
CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)713 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
714 {
715 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
716 }
717 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK			0x00000800
718 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT			11
CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)719 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
720 {
721 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
722 }
723 #define CP_DRAW_INDX_2_1_NOT_EOP				0x00001000
724 #define CP_DRAW_INDX_2_1_SMALL_INDEX				0x00002000
725 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
726 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK			0xff000000
727 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT			24
CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)728 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
729 {
730 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
731 }
732 
733 #define REG_CP_DRAW_INDX_2_2					0x00000002
734 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK			0xffffffff
735 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT			0
CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)736 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
737 {
738 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
739 }
740 
741 #define REG_CP_DRAW_INDX_OFFSET_0				0x00000000
742 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK			0x0000003f
743 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT			0
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)744 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
745 {
746 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
747 }
748 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK		0x000000c0
749 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT		6
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)750 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
751 {
752 	return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
753 }
754 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK			0x00000300
755 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT			8
CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)756 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
757 {
758 	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
759 }
760 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK			0x00000c00
761 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT			10
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)762 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
763 {
764 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
765 }
766 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK			0x00003000
767 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT			12
CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)768 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
769 {
770 	return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
771 }
772 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE				0x00010000
773 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE			0x00020000
774 
775 #define REG_CP_DRAW_INDX_OFFSET_1				0x00000001
776 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK		0xffffffff
777 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT		0
CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)778 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
779 {
780 	return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
781 }
782 
783 #define REG_CP_DRAW_INDX_OFFSET_2				0x00000002
784 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK			0xffffffff
785 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT		0
CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)786 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
787 {
788 	return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
789 }
790 
791 #define REG_CP_DRAW_INDX_OFFSET_3				0x00000003
792 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK			0xffffffff
793 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT			0
CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)794 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
795 {
796 	return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
797 }
798 
799 
800 #define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
801 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK		0xffffffff
802 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT		0
CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)803 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
804 {
805 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
806 }
807 
808 #define REG_CP_DRAW_INDX_OFFSET_5				0x00000005
809 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK		0xffffffff
810 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT		0
CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)811 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
812 {
813 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
814 }
815 
816 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE			0x00000004
817 
818 #define REG_CP_DRAW_INDX_OFFSET_6				0x00000006
819 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK			0xffffffff
820 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT		0
CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)821 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
822 {
823 	return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
824 }
825 
826 #define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
827 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK			0xffffffff
828 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT			0
CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)829 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
830 {
831 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
832 }
833 
834 #define REG_CP_DRAW_INDX_OFFSET_5				0x00000005
835 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK			0xffffffff
836 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT			0
CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)837 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
838 {
839 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
840 }
841 
842 #define REG_A4XX_CP_DRAW_INDIRECT_0				0x00000000
843 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK			0x0000003f
844 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT		0
A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)845 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
846 {
847 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
848 }
849 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK		0x000000c0
850 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT		6
A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)851 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
852 {
853 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
854 }
855 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK			0x00000300
856 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT			8
A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)857 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
858 {
859 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
860 }
861 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK		0x00000c00
862 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT		10
A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)863 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
864 {
865 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
866 }
867 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK		0x00003000
868 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT		12
A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)869 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
870 {
871 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
872 }
873 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE			0x00010000
874 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE			0x00020000
875 
876 
877 #define REG_A4XX_CP_DRAW_INDIRECT_1				0x00000001
878 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK			0xffffffff
879 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT			0
A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)880 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
881 {
882 	return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
883 }
884 
885 
886 #define REG_A5XX_CP_DRAW_INDIRECT_1				0x00000001
887 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK		0xffffffff
888 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT		0
A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)889 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
890 {
891 	return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
892 }
893 
894 #define REG_A5XX_CP_DRAW_INDIRECT_2				0x00000002
895 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK		0xffffffff
896 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT		0
A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)897 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
898 {
899 	return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
900 }
901 
902 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT			0x00000001
903 
904 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0			0x00000000
905 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK		0x0000003f
906 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)907 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
908 {
909 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
910 }
911 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK	0x000000c0
912 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT	6
A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)913 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
914 {
915 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
916 }
917 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK		0x00000300
918 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT		8
A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)919 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
920 {
921 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
922 }
923 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK		0x00000c00
924 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT		10
A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)925 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
926 {
927 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
928 }
929 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK		0x00003000
930 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT		12
A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)931 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
932 {
933 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
934 }
935 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE			0x00010000
936 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE		0x00020000
937 
938 
939 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1			0x00000001
940 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK		0xffffffff
941 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)942 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
943 {
944 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
945 }
946 
947 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2			0x00000002
948 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK		0xffffffff
949 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)950 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
951 {
952 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
953 }
954 
955 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3			0x00000003
956 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK		0xffffffff
957 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)958 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
959 {
960 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
961 }
962 
963 
964 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1			0x00000001
965 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK		0xffffffff
966 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT	0
A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)967 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
968 {
969 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
970 }
971 
972 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2			0x00000002
973 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK		0xffffffff
974 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT	0
A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)975 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
976 {
977 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
978 }
979 
980 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE		0x00000001
981 
982 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3			0x00000003
983 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK		0xffffffff
984 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT		0
A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)985 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
986 {
987 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
988 }
989 
990 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4			0x00000004
991 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK		0xffffffff
992 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT		0
A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)993 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
994 {
995 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
996 }
997 
998 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5			0x00000005
999 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK		0xffffffff
1000 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT		0
A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)1001 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
1002 {
1003 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
1004 }
1005 
1006 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT			0x00000004
1007 
1008 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0			0x00000000
1009 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK		0x0000003f
1010 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT		0
A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)1011 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
1012 {
1013 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
1014 }
1015 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK	0x000000c0
1016 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT	6
A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)1017 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
1018 {
1019 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
1020 }
1021 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK		0x00000300
1022 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT		8
A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)1023 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1024 {
1025 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
1026 }
1027 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK		0x00000c00
1028 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT		10
A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)1029 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
1030 {
1031 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
1032 }
1033 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK		0x00003000
1034 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT		12
A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)1035 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
1036 {
1037 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
1038 }
1039 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE			0x00010000
1040 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE		0x00020000
1041 
1042 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1			0x00000001
1043 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK		0x0000000f
1044 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT		0
A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)1045 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
1046 {
1047 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
1048 }
1049 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK		0x003fff00
1050 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT		8
A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)1051 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
1052 {
1053 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1054 }
1055 
1056 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT		0x00000002
1057 
1058 
1059 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT		0x00000003
1060 
1061 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE			0x00000005
1062 
1063 
1064 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED		0x00000003
1065 
1066 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED		0x00000005
1067 
1068 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED		0x00000006
1069 
1070 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED		0x00000008
1071 
1072 
1073 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT		0x00000003
1074 
1075 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT	0x00000005
1076 
1077 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT		0x00000007
1078 
1079 
1080 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED	0x00000003
1081 
1082 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED	0x00000005
1083 
1084 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED	0x00000006
1085 
1086 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED	0x00000008
1087 
1088 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED	0x0000000a
1089 
1090 #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0			0x00000000
1091 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE			0x00000001
1092 
1093 #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0				0x00000000
1094 #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE			0x00000001
1095 
1096 #define REG_CP_DRAW_PRED_SET_0					0x00000000
1097 #define CP_DRAW_PRED_SET_0_SRC__MASK				0x000000f0
1098 #define CP_DRAW_PRED_SET_0_SRC__SHIFT				4
CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)1099 static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
1100 {
1101 	return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
1102 }
1103 #define CP_DRAW_PRED_SET_0_TEST__MASK				0x00000100
1104 #define CP_DRAW_PRED_SET_0_TEST__SHIFT				8
CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)1105 static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
1106 {
1107 	return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
1108 }
1109 
1110 #define REG_CP_DRAW_PRED_SET_MEM_ADDR				0x00000001
1111 
REG_CP_SET_DRAW_STATE_(uint32_t i0)1112 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1113 
REG_CP_SET_DRAW_STATE__0(uint32_t i0)1114 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1115 #define CP_SET_DRAW_STATE__0_COUNT__MASK			0x0000ffff
1116 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT			0
CP_SET_DRAW_STATE__0_COUNT(uint32_t val)1117 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
1118 {
1119 	return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
1120 }
1121 #define CP_SET_DRAW_STATE__0_DIRTY				0x00010000
1122 #define CP_SET_DRAW_STATE__0_DISABLE				0x00020000
1123 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS			0x00040000
1124 #define CP_SET_DRAW_STATE__0_LOAD_IMMED				0x00080000
1125 #define CP_SET_DRAW_STATE__0_BINNING				0x00100000
1126 #define CP_SET_DRAW_STATE__0_GMEM				0x00200000
1127 #define CP_SET_DRAW_STATE__0_SYSMEM				0x00400000
1128 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK			0x1f000000
1129 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT			24
CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)1130 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
1131 {
1132 	return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
1133 }
1134 
REG_CP_SET_DRAW_STATE__1(uint32_t i0)1135 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1136 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK			0xffffffff
1137 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT			0
CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)1138 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
1139 {
1140 	return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
1141 }
1142 
REG_CP_SET_DRAW_STATE__2(uint32_t i0)1143 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1144 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK			0xffffffff
1145 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT			0
CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)1146 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
1147 {
1148 	return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
1149 }
1150 
1151 #define REG_CP_SET_BIN_0					0x00000000
1152 
1153 #define REG_CP_SET_BIN_1					0x00000001
1154 #define CP_SET_BIN_1_X1__MASK					0x0000ffff
1155 #define CP_SET_BIN_1_X1__SHIFT					0
CP_SET_BIN_1_X1(uint32_t val)1156 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
1157 {
1158 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
1159 }
1160 #define CP_SET_BIN_1_Y1__MASK					0xffff0000
1161 #define CP_SET_BIN_1_Y1__SHIFT					16
CP_SET_BIN_1_Y1(uint32_t val)1162 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
1163 {
1164 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
1165 }
1166 
1167 #define REG_CP_SET_BIN_2					0x00000002
1168 #define CP_SET_BIN_2_X2__MASK					0x0000ffff
1169 #define CP_SET_BIN_2_X2__SHIFT					0
CP_SET_BIN_2_X2(uint32_t val)1170 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
1171 {
1172 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
1173 }
1174 #define CP_SET_BIN_2_Y2__MASK					0xffff0000
1175 #define CP_SET_BIN_2_Y2__SHIFT					16
CP_SET_BIN_2_Y2(uint32_t val)1176 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
1177 {
1178 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
1179 }
1180 
1181 #define REG_CP_SET_BIN_DATA_0					0x00000000
1182 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK			0xffffffff
1183 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT			0
CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)1184 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
1185 {
1186 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
1187 }
1188 
1189 #define REG_CP_SET_BIN_DATA_1					0x00000001
1190 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK		0xffffffff
1191 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT		0
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)1192 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
1193 {
1194 	return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
1195 }
1196 
1197 #define REG_CP_SET_BIN_DATA5_0					0x00000000
1198 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK			0x003f0000
1199 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT			16
CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)1200 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
1201 {
1202 	return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
1203 }
1204 #define CP_SET_BIN_DATA5_0_VSC_N__MASK				0x07c00000
1205 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT				22
CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)1206 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
1207 {
1208 	return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
1209 }
1210 
1211 #define REG_CP_SET_BIN_DATA5_1					0x00000001
1212 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK		0xffffffff
1213 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT		0
CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)1214 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
1215 {
1216 	return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
1217 }
1218 
1219 #define REG_CP_SET_BIN_DATA5_2					0x00000002
1220 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK		0xffffffff
1221 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT		0
CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)1222 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
1223 {
1224 	return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
1225 }
1226 
1227 #define REG_CP_SET_BIN_DATA5_3					0x00000003
1228 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK		0xffffffff
1229 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT		0
CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)1230 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
1231 {
1232 	return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
1233 }
1234 
1235 #define REG_CP_SET_BIN_DATA5_4					0x00000004
1236 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK		0xffffffff
1237 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT		0
CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)1238 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
1239 {
1240 	return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
1241 }
1242 
1243 #define REG_CP_SET_BIN_DATA5_5					0x00000005
1244 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK		0xffffffff
1245 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT		0
CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)1246 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
1247 {
1248 	return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
1249 }
1250 
1251 #define REG_CP_SET_BIN_DATA5_6					0x00000006
1252 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK		0xffffffff
1253 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT		0
CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)1254 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
1255 {
1256 	return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
1257 }
1258 
1259 #define REG_CP_SET_BIN_DATA5_OFFSET_0				0x00000000
1260 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK		0x003f0000
1261 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT		16
CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)1262 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
1263 {
1264 	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
1265 }
1266 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK			0x07c00000
1267 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT			22
CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)1268 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
1269 {
1270 	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
1271 }
1272 
1273 #define REG_CP_SET_BIN_DATA5_OFFSET_1				0x00000001
1274 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK		0xffffffff
1275 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT	0
CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)1276 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
1277 {
1278 	return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
1279 }
1280 
1281 #define REG_CP_SET_BIN_DATA5_OFFSET_2				0x00000002
1282 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK		0xffffffff
1283 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT	0
CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)1284 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
1285 {
1286 	return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
1287 }
1288 
1289 #define REG_CP_SET_BIN_DATA5_OFFSET_3				0x00000003
1290 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK	0xffffffff
1291 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT	0
CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)1292 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
1293 {
1294 	return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
1295 }
1296 
1297 #define REG_CP_REG_RMW_0					0x00000000
1298 #define CP_REG_RMW_0_DST_REG__MASK				0x0003ffff
1299 #define CP_REG_RMW_0_DST_REG__SHIFT				0
CP_REG_RMW_0_DST_REG(uint32_t val)1300 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
1301 {
1302 	return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
1303 }
1304 #define CP_REG_RMW_0_ROTATE__MASK				0x1f000000
1305 #define CP_REG_RMW_0_ROTATE__SHIFT				24
CP_REG_RMW_0_ROTATE(uint32_t val)1306 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
1307 {
1308 	return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
1309 }
1310 #define CP_REG_RMW_0_SRC1_ADD					0x20000000
1311 #define CP_REG_RMW_0_SRC1_IS_REG				0x40000000
1312 #define CP_REG_RMW_0_SRC0_IS_REG				0x80000000
1313 
1314 #define REG_CP_REG_RMW_1					0x00000001
1315 #define CP_REG_RMW_1_SRC0__MASK					0xffffffff
1316 #define CP_REG_RMW_1_SRC0__SHIFT				0
CP_REG_RMW_1_SRC0(uint32_t val)1317 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
1318 {
1319 	return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
1320 }
1321 
1322 #define REG_CP_REG_RMW_2					0x00000002
1323 #define CP_REG_RMW_2_SRC1__MASK					0xffffffff
1324 #define CP_REG_RMW_2_SRC1__SHIFT				0
CP_REG_RMW_2_SRC1(uint32_t val)1325 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
1326 {
1327 	return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
1328 }
1329 
1330 #define REG_CP_REG_TO_MEM_0					0x00000000
1331 #define CP_REG_TO_MEM_0_REG__MASK				0x0003ffff
1332 #define CP_REG_TO_MEM_0_REG__SHIFT				0
CP_REG_TO_MEM_0_REG(uint32_t val)1333 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
1334 {
1335 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
1336 }
1337 #define CP_REG_TO_MEM_0_CNT__MASK				0x3ffc0000
1338 #define CP_REG_TO_MEM_0_CNT__SHIFT				18
CP_REG_TO_MEM_0_CNT(uint32_t val)1339 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
1340 {
1341 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1342 }
1343 #define CP_REG_TO_MEM_0_64B					0x40000000
1344 #define CP_REG_TO_MEM_0_ACCUMULATE				0x80000000
1345 
1346 #define REG_CP_REG_TO_MEM_1					0x00000001
1347 #define CP_REG_TO_MEM_1_DEST__MASK				0xffffffff
1348 #define CP_REG_TO_MEM_1_DEST__SHIFT				0
CP_REG_TO_MEM_1_DEST(uint32_t val)1349 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1350 {
1351 	return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1352 }
1353 
1354 #define REG_CP_REG_TO_MEM_2					0x00000002
1355 #define CP_REG_TO_MEM_2_DEST_HI__MASK				0xffffffff
1356 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT				0
CP_REG_TO_MEM_2_DEST_HI(uint32_t val)1357 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1358 {
1359 	return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1360 }
1361 
1362 #define REG_CP_REG_TO_MEM_OFFSET_REG_0				0x00000000
1363 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK			0x0003ffff
1364 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT			0
CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)1365 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
1366 {
1367 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
1368 }
1369 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK			0x3ffc0000
1370 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT			18
CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)1371 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
1372 {
1373 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
1374 }
1375 #define CP_REG_TO_MEM_OFFSET_REG_0_64B				0x40000000
1376 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE			0x80000000
1377 
1378 #define REG_CP_REG_TO_MEM_OFFSET_REG_1				0x00000001
1379 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK			0xffffffff
1380 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT			0
CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)1381 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
1382 {
1383 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
1384 }
1385 
1386 #define REG_CP_REG_TO_MEM_OFFSET_REG_2				0x00000002
1387 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK		0xffffffff
1388 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT		0
CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)1389 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
1390 {
1391 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
1392 }
1393 
1394 #define REG_CP_REG_TO_MEM_OFFSET_REG_3				0x00000003
1395 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK		0x0003ffff
1396 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT		0
CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)1397 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
1398 {
1399 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
1400 }
1401 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH		0x00080000
1402 
1403 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0				0x00000000
1404 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK			0x0003ffff
1405 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT			0
CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)1406 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
1407 {
1408 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
1409 }
1410 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK			0x3ffc0000
1411 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT			18
CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)1412 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
1413 {
1414 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
1415 }
1416 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B				0x40000000
1417 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE			0x80000000
1418 
1419 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1				0x00000001
1420 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK			0xffffffff
1421 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT			0
CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)1422 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
1423 {
1424 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
1425 }
1426 
1427 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2				0x00000002
1428 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK		0xffffffff
1429 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT		0
CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)1430 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
1431 {
1432 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
1433 }
1434 
1435 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3				0x00000003
1436 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK		0xffffffff
1437 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT		0
CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)1438 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
1439 {
1440 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
1441 }
1442 
1443 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4				0x00000004
1444 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK		0xffffffff
1445 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT		0
CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)1446 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
1447 {
1448 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
1449 }
1450 
1451 #define REG_CP_MEM_TO_REG_0					0x00000000
1452 #define CP_MEM_TO_REG_0_REG__MASK				0x0003ffff
1453 #define CP_MEM_TO_REG_0_REG__SHIFT				0
CP_MEM_TO_REG_0_REG(uint32_t val)1454 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1455 {
1456 	return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1457 }
1458 #define CP_MEM_TO_REG_0_CNT__MASK				0x3ff80000
1459 #define CP_MEM_TO_REG_0_CNT__SHIFT				19
CP_MEM_TO_REG_0_CNT(uint32_t val)1460 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1461 {
1462 	return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1463 }
1464 #define CP_MEM_TO_REG_0_SHIFT_BY_2				0x40000000
1465 #define CP_MEM_TO_REG_0_UNK31					0x80000000
1466 
1467 #define REG_CP_MEM_TO_REG_1					0x00000001
1468 #define CP_MEM_TO_REG_1_SRC__MASK				0xffffffff
1469 #define CP_MEM_TO_REG_1_SRC__SHIFT				0
CP_MEM_TO_REG_1_SRC(uint32_t val)1470 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1471 {
1472 	return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1473 }
1474 
1475 #define REG_CP_MEM_TO_REG_2					0x00000002
1476 #define CP_MEM_TO_REG_2_SRC_HI__MASK				0xffffffff
1477 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT				0
CP_MEM_TO_REG_2_SRC_HI(uint32_t val)1478 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1479 {
1480 	return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1481 }
1482 
1483 #define REG_CP_MEM_TO_MEM_0					0x00000000
1484 #define CP_MEM_TO_MEM_0_NEG_A					0x00000001
1485 #define CP_MEM_TO_MEM_0_NEG_B					0x00000002
1486 #define CP_MEM_TO_MEM_0_NEG_C					0x00000004
1487 #define CP_MEM_TO_MEM_0_DOUBLE					0x20000000
1488 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES			0x40000000
1489 #define CP_MEM_TO_MEM_0_UNK31					0x80000000
1490 
1491 #define REG_CP_MEMCPY_0						0x00000000
1492 #define CP_MEMCPY_0_DWORDS__MASK				0xffffffff
1493 #define CP_MEMCPY_0_DWORDS__SHIFT				0
CP_MEMCPY_0_DWORDS(uint32_t val)1494 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
1495 {
1496 	return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
1497 }
1498 
1499 #define REG_CP_MEMCPY_1						0x00000001
1500 #define CP_MEMCPY_1_SRC_LO__MASK				0xffffffff
1501 #define CP_MEMCPY_1_SRC_LO__SHIFT				0
CP_MEMCPY_1_SRC_LO(uint32_t val)1502 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
1503 {
1504 	return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
1505 }
1506 
1507 #define REG_CP_MEMCPY_2						0x00000002
1508 #define CP_MEMCPY_2_SRC_HI__MASK				0xffffffff
1509 #define CP_MEMCPY_2_SRC_HI__SHIFT				0
CP_MEMCPY_2_SRC_HI(uint32_t val)1510 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
1511 {
1512 	return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
1513 }
1514 
1515 #define REG_CP_MEMCPY_3						0x00000003
1516 #define CP_MEMCPY_3_DST_LO__MASK				0xffffffff
1517 #define CP_MEMCPY_3_DST_LO__SHIFT				0
CP_MEMCPY_3_DST_LO(uint32_t val)1518 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
1519 {
1520 	return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
1521 }
1522 
1523 #define REG_CP_MEMCPY_4						0x00000004
1524 #define CP_MEMCPY_4_DST_HI__MASK				0xffffffff
1525 #define CP_MEMCPY_4_DST_HI__SHIFT				0
CP_MEMCPY_4_DST_HI(uint32_t val)1526 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
1527 {
1528 	return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
1529 }
1530 
1531 #define REG_CP_REG_TO_SCRATCH_0					0x00000000
1532 #define CP_REG_TO_SCRATCH_0_REG__MASK				0x0003ffff
1533 #define CP_REG_TO_SCRATCH_0_REG__SHIFT				0
CP_REG_TO_SCRATCH_0_REG(uint32_t val)1534 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
1535 {
1536 	return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
1537 }
1538 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK			0x00700000
1539 #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT			20
CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)1540 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
1541 {
1542 	return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
1543 }
1544 #define CP_REG_TO_SCRATCH_0_CNT__MASK				0x07000000
1545 #define CP_REG_TO_SCRATCH_0_CNT__SHIFT				24
CP_REG_TO_SCRATCH_0_CNT(uint32_t val)1546 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
1547 {
1548 	return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
1549 }
1550 
1551 #define REG_CP_SCRATCH_TO_REG_0					0x00000000
1552 #define CP_SCRATCH_TO_REG_0_REG__MASK				0x0003ffff
1553 #define CP_SCRATCH_TO_REG_0_REG__SHIFT				0
CP_SCRATCH_TO_REG_0_REG(uint32_t val)1554 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
1555 {
1556 	return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
1557 }
1558 #define CP_SCRATCH_TO_REG_0_UNK18				0x00040000
1559 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK			0x00700000
1560 #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT			20
CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)1561 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
1562 {
1563 	return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
1564 }
1565 #define CP_SCRATCH_TO_REG_0_CNT__MASK				0x07000000
1566 #define CP_SCRATCH_TO_REG_0_CNT__SHIFT				24
CP_SCRATCH_TO_REG_0_CNT(uint32_t val)1567 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
1568 {
1569 	return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
1570 }
1571 
1572 #define REG_CP_SCRATCH_WRITE_0					0x00000000
1573 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK			0x00700000
1574 #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT			20
CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)1575 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
1576 {
1577 	return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
1578 }
1579 
1580 #define REG_CP_MEM_WRITE_0					0x00000000
1581 #define CP_MEM_WRITE_0_ADDR_LO__MASK				0xffffffff
1582 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT				0
CP_MEM_WRITE_0_ADDR_LO(uint32_t val)1583 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
1584 {
1585 	return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
1586 }
1587 
1588 #define REG_CP_MEM_WRITE_1					0x00000001
1589 #define CP_MEM_WRITE_1_ADDR_HI__MASK				0xffffffff
1590 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT				0
CP_MEM_WRITE_1_ADDR_HI(uint32_t val)1591 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
1592 {
1593 	return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
1594 }
1595 
1596 #define REG_CP_COND_WRITE_0					0x00000000
1597 #define CP_COND_WRITE_0_FUNCTION__MASK				0x00000007
1598 #define CP_COND_WRITE_0_FUNCTION__SHIFT				0
CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)1599 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1600 {
1601 	return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1602 }
1603 #define CP_COND_WRITE_0_POLL_MEMORY				0x00000010
1604 #define CP_COND_WRITE_0_WRITE_MEMORY				0x00000100
1605 
1606 #define REG_CP_COND_WRITE_1					0x00000001
1607 #define CP_COND_WRITE_1_POLL_ADDR__MASK				0xffffffff
1608 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT			0
CP_COND_WRITE_1_POLL_ADDR(uint32_t val)1609 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1610 {
1611 	return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1612 }
1613 
1614 #define REG_CP_COND_WRITE_2					0x00000002
1615 #define CP_COND_WRITE_2_REF__MASK				0xffffffff
1616 #define CP_COND_WRITE_2_REF__SHIFT				0
CP_COND_WRITE_2_REF(uint32_t val)1617 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1618 {
1619 	return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1620 }
1621 
1622 #define REG_CP_COND_WRITE_3					0x00000003
1623 #define CP_COND_WRITE_3_MASK__MASK				0xffffffff
1624 #define CP_COND_WRITE_3_MASK__SHIFT				0
CP_COND_WRITE_3_MASK(uint32_t val)1625 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1626 {
1627 	return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1628 }
1629 
1630 #define REG_CP_COND_WRITE_4					0x00000004
1631 #define CP_COND_WRITE_4_WRITE_ADDR__MASK			0xffffffff
1632 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT			0
CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)1633 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1634 {
1635 	return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1636 }
1637 
1638 #define REG_CP_COND_WRITE_5					0x00000005
1639 #define CP_COND_WRITE_5_WRITE_DATA__MASK			0xffffffff
1640 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT			0
CP_COND_WRITE_5_WRITE_DATA(uint32_t val)1641 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1642 {
1643 	return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1644 }
1645 
1646 #define REG_CP_COND_WRITE5_0					0x00000000
1647 #define CP_COND_WRITE5_0_FUNCTION__MASK				0x00000007
1648 #define CP_COND_WRITE5_0_FUNCTION__SHIFT			0
CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)1649 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1650 {
1651 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1652 }
1653 #define CP_COND_WRITE5_0_SIGNED_COMPARE				0x00000008
1654 #define CP_COND_WRITE5_0_POLL_MEMORY				0x00000010
1655 #define CP_COND_WRITE5_0_POLL_SCRATCH				0x00000020
1656 #define CP_COND_WRITE5_0_WRITE_MEMORY				0x00000100
1657 
1658 #define REG_CP_COND_WRITE5_1					0x00000001
1659 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK			0xffffffff
1660 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT			0
CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)1661 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1662 {
1663 	return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1664 }
1665 
1666 #define REG_CP_COND_WRITE5_2					0x00000002
1667 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK			0xffffffff
1668 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT			0
CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)1669 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1670 {
1671 	return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1672 }
1673 
1674 #define REG_CP_COND_WRITE5_3					0x00000003
1675 #define CP_COND_WRITE5_3_REF__MASK				0xffffffff
1676 #define CP_COND_WRITE5_3_REF__SHIFT				0
CP_COND_WRITE5_3_REF(uint32_t val)1677 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1678 {
1679 	return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1680 }
1681 
1682 #define REG_CP_COND_WRITE5_4					0x00000004
1683 #define CP_COND_WRITE5_4_MASK__MASK				0xffffffff
1684 #define CP_COND_WRITE5_4_MASK__SHIFT				0
CP_COND_WRITE5_4_MASK(uint32_t val)1685 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1686 {
1687 	return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1688 }
1689 
1690 #define REG_CP_COND_WRITE5_5					0x00000005
1691 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK			0xffffffff
1692 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT			0
CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)1693 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1694 {
1695 	return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1696 }
1697 
1698 #define REG_CP_COND_WRITE5_6					0x00000006
1699 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK			0xffffffff
1700 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT			0
CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)1701 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1702 {
1703 	return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1704 }
1705 
1706 #define REG_CP_COND_WRITE5_7					0x00000007
1707 #define CP_COND_WRITE5_7_WRITE_DATA__MASK			0xffffffff
1708 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT			0
CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)1709 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1710 {
1711 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1712 }
1713 
1714 #define REG_CP_WAIT_MEM_GTE_0					0x00000000
1715 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK			0xffffffff
1716 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT			0
CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)1717 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
1718 {
1719 	return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
1720 }
1721 
1722 #define REG_CP_WAIT_MEM_GTE_1					0x00000001
1723 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK			0xffffffff
1724 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT			0
CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)1725 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
1726 {
1727 	return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
1728 }
1729 
1730 #define REG_CP_WAIT_MEM_GTE_2					0x00000002
1731 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK			0xffffffff
1732 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT			0
CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)1733 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
1734 {
1735 	return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
1736 }
1737 
1738 #define REG_CP_WAIT_MEM_GTE_3					0x00000003
1739 #define CP_WAIT_MEM_GTE_3_REF__MASK				0xffffffff
1740 #define CP_WAIT_MEM_GTE_3_REF__SHIFT				0
CP_WAIT_MEM_GTE_3_REF(uint32_t val)1741 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
1742 {
1743 	return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
1744 }
1745 
1746 #define REG_CP_WAIT_REG_MEM_0					0x00000000
1747 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK			0x00000007
1748 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT			0
CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)1749 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
1750 {
1751 	return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
1752 }
1753 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE			0x00000008
1754 #define CP_WAIT_REG_MEM_0_POLL_MEMORY				0x00000010
1755 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH				0x00000020
1756 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY				0x00000100
1757 
1758 #define REG_CP_WAIT_REG_MEM_1					0x00000001
1759 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK			0xffffffff
1760 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT			0
CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)1761 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
1762 {
1763 	return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
1764 }
1765 
1766 #define REG_CP_WAIT_REG_MEM_2					0x00000002
1767 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK			0xffffffff
1768 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT			0
CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)1769 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
1770 {
1771 	return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
1772 }
1773 
1774 #define REG_CP_WAIT_REG_MEM_3					0x00000003
1775 #define CP_WAIT_REG_MEM_3_REF__MASK				0xffffffff
1776 #define CP_WAIT_REG_MEM_3_REF__SHIFT				0
CP_WAIT_REG_MEM_3_REF(uint32_t val)1777 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
1778 {
1779 	return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
1780 }
1781 
1782 #define REG_CP_WAIT_REG_MEM_4					0x00000004
1783 #define CP_WAIT_REG_MEM_4_MASK__MASK				0xffffffff
1784 #define CP_WAIT_REG_MEM_4_MASK__SHIFT				0
CP_WAIT_REG_MEM_4_MASK(uint32_t val)1785 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
1786 {
1787 	return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
1788 }
1789 
1790 #define REG_CP_WAIT_REG_MEM_5					0x00000005
1791 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK		0xffffffff
1792 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT		0
CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)1793 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
1794 {
1795 	return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
1796 }
1797 
1798 #define REG_CP_WAIT_TWO_REGS_0					0x00000000
1799 #define CP_WAIT_TWO_REGS_0_REG0__MASK				0x0003ffff
1800 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT				0
CP_WAIT_TWO_REGS_0_REG0(uint32_t val)1801 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
1802 {
1803 	return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
1804 }
1805 
1806 #define REG_CP_WAIT_TWO_REGS_1					0x00000001
1807 #define CP_WAIT_TWO_REGS_1_REG1__MASK				0x0003ffff
1808 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT				0
CP_WAIT_TWO_REGS_1_REG1(uint32_t val)1809 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
1810 {
1811 	return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
1812 }
1813 
1814 #define REG_CP_WAIT_TWO_REGS_2					0x00000002
1815 #define CP_WAIT_TWO_REGS_2_REF__MASK				0xffffffff
1816 #define CP_WAIT_TWO_REGS_2_REF__SHIFT				0
CP_WAIT_TWO_REGS_2_REF(uint32_t val)1817 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
1818 {
1819 	return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
1820 }
1821 
1822 #define REG_CP_DISPATCH_COMPUTE_0				0x00000000
1823 
1824 #define REG_CP_DISPATCH_COMPUTE_1				0x00000001
1825 #define CP_DISPATCH_COMPUTE_1_X__MASK				0xffffffff
1826 #define CP_DISPATCH_COMPUTE_1_X__SHIFT				0
CP_DISPATCH_COMPUTE_1_X(uint32_t val)1827 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1828 {
1829 	return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1830 }
1831 
1832 #define REG_CP_DISPATCH_COMPUTE_2				0x00000002
1833 #define CP_DISPATCH_COMPUTE_2_Y__MASK				0xffffffff
1834 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT				0
CP_DISPATCH_COMPUTE_2_Y(uint32_t val)1835 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1836 {
1837 	return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1838 }
1839 
1840 #define REG_CP_DISPATCH_COMPUTE_3				0x00000003
1841 #define CP_DISPATCH_COMPUTE_3_Z__MASK				0xffffffff
1842 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT				0
CP_DISPATCH_COMPUTE_3_Z(uint32_t val)1843 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1844 {
1845 	return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1846 }
1847 
1848 #define REG_CP_SET_RENDER_MODE_0				0x00000000
1849 #define CP_SET_RENDER_MODE_0_MODE__MASK				0x000001ff
1850 #define CP_SET_RENDER_MODE_0_MODE__SHIFT			0
CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)1851 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1852 {
1853 	return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1854 }
1855 
1856 #define REG_CP_SET_RENDER_MODE_1				0x00000001
1857 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK			0xffffffff
1858 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT			0
CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)1859 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1860 {
1861 	return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1862 }
1863 
1864 #define REG_CP_SET_RENDER_MODE_2				0x00000002
1865 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK			0xffffffff
1866 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT			0
CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)1867 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1868 {
1869 	return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1870 }
1871 
1872 #define REG_CP_SET_RENDER_MODE_3				0x00000003
1873 #define CP_SET_RENDER_MODE_3_VSC_ENABLE				0x00000008
1874 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE			0x00000010
1875 
1876 #define REG_CP_SET_RENDER_MODE_4				0x00000004
1877 
1878 #define REG_CP_SET_RENDER_MODE_5				0x00000005
1879 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK			0xffffffff
1880 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT			0
CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)1881 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1882 {
1883 	return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1884 }
1885 
1886 #define REG_CP_SET_RENDER_MODE_6				0x00000006
1887 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK			0xffffffff
1888 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT			0
CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)1889 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1890 {
1891 	return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1892 }
1893 
1894 #define REG_CP_SET_RENDER_MODE_7				0x00000007
1895 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK			0xffffffff
1896 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT			0
CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)1897 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1898 {
1899 	return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1900 }
1901 
1902 #define REG_CP_COMPUTE_CHECKPOINT_0				0x00000000
1903 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK			0xffffffff
1904 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT		0
CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)1905 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1906 {
1907 	return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1908 }
1909 
1910 #define REG_CP_COMPUTE_CHECKPOINT_1				0x00000001
1911 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK			0xffffffff
1912 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT		0
CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)1913 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1914 {
1915 	return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1916 }
1917 
1918 #define REG_CP_COMPUTE_CHECKPOINT_2				0x00000002
1919 
1920 #define REG_CP_COMPUTE_CHECKPOINT_3				0x00000003
1921 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK		0xffffffff
1922 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT		0
CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)1923 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1924 {
1925 	return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1926 }
1927 
1928 #define REG_CP_COMPUTE_CHECKPOINT_4				0x00000004
1929 
1930 #define REG_CP_COMPUTE_CHECKPOINT_5				0x00000005
1931 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK			0xffffffff
1932 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT		0
CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)1933 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1934 {
1935 	return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1936 }
1937 
1938 #define REG_CP_COMPUTE_CHECKPOINT_6				0x00000006
1939 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK			0xffffffff
1940 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT		0
CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)1941 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1942 {
1943 	return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1944 }
1945 
1946 #define REG_CP_COMPUTE_CHECKPOINT_7				0x00000007
1947 
1948 #define REG_CP_PERFCOUNTER_ACTION_0				0x00000000
1949 
1950 #define REG_CP_PERFCOUNTER_ACTION_1				0x00000001
1951 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK			0xffffffff
1952 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT		0
CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)1953 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1954 {
1955 	return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1956 }
1957 
1958 #define REG_CP_PERFCOUNTER_ACTION_2				0x00000002
1959 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK			0xffffffff
1960 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT		0
CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)1961 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1962 {
1963 	return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1964 }
1965 
1966 #define REG_CP_EVENT_WRITE_0					0x00000000
1967 #define CP_EVENT_WRITE_0_EVENT__MASK				0x000000ff
1968 #define CP_EVENT_WRITE_0_EVENT__SHIFT				0
CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)1969 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1970 {
1971 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1972 }
1973 #define CP_EVENT_WRITE_0_TIMESTAMP				0x40000000
1974 #define CP_EVENT_WRITE_0_IRQ					0x80000000
1975 
1976 #define REG_CP_EVENT_WRITE_1					0x00000001
1977 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK			0xffffffff
1978 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT			0
CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)1979 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1980 {
1981 	return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1982 }
1983 
1984 #define REG_CP_EVENT_WRITE_2					0x00000002
1985 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK			0xffffffff
1986 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT			0
CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)1987 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1988 {
1989 	return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1990 }
1991 
1992 #define REG_CP_EVENT_WRITE_3					0x00000003
1993 
1994 #define REG_CP_BLIT_0						0x00000000
1995 #define CP_BLIT_0_OP__MASK					0x0000000f
1996 #define CP_BLIT_0_OP__SHIFT					0
CP_BLIT_0_OP(enum cp_blit_cmd val)1997 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1998 {
1999 	return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
2000 }
2001 
2002 #define REG_CP_BLIT_1						0x00000001
2003 #define CP_BLIT_1_SRC_X1__MASK					0x00003fff
2004 #define CP_BLIT_1_SRC_X1__SHIFT					0
CP_BLIT_1_SRC_X1(uint32_t val)2005 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
2006 {
2007 	return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
2008 }
2009 #define CP_BLIT_1_SRC_Y1__MASK					0x3fff0000
2010 #define CP_BLIT_1_SRC_Y1__SHIFT					16
CP_BLIT_1_SRC_Y1(uint32_t val)2011 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
2012 {
2013 	return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
2014 }
2015 
2016 #define REG_CP_BLIT_2						0x00000002
2017 #define CP_BLIT_2_SRC_X2__MASK					0x00003fff
2018 #define CP_BLIT_2_SRC_X2__SHIFT					0
CP_BLIT_2_SRC_X2(uint32_t val)2019 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
2020 {
2021 	return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
2022 }
2023 #define CP_BLIT_2_SRC_Y2__MASK					0x3fff0000
2024 #define CP_BLIT_2_SRC_Y2__SHIFT					16
CP_BLIT_2_SRC_Y2(uint32_t val)2025 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
2026 {
2027 	return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
2028 }
2029 
2030 #define REG_CP_BLIT_3						0x00000003
2031 #define CP_BLIT_3_DST_X1__MASK					0x00003fff
2032 #define CP_BLIT_3_DST_X1__SHIFT					0
CP_BLIT_3_DST_X1(uint32_t val)2033 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
2034 {
2035 	return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
2036 }
2037 #define CP_BLIT_3_DST_Y1__MASK					0x3fff0000
2038 #define CP_BLIT_3_DST_Y1__SHIFT					16
CP_BLIT_3_DST_Y1(uint32_t val)2039 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
2040 {
2041 	return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
2042 }
2043 
2044 #define REG_CP_BLIT_4						0x00000004
2045 #define CP_BLIT_4_DST_X2__MASK					0x00003fff
2046 #define CP_BLIT_4_DST_X2__SHIFT					0
CP_BLIT_4_DST_X2(uint32_t val)2047 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
2048 {
2049 	return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
2050 }
2051 #define CP_BLIT_4_DST_Y2__MASK					0x3fff0000
2052 #define CP_BLIT_4_DST_Y2__SHIFT					16
CP_BLIT_4_DST_Y2(uint32_t val)2053 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
2054 {
2055 	return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
2056 }
2057 
2058 #define REG_CP_EXEC_CS_0					0x00000000
2059 
2060 #define REG_CP_EXEC_CS_1					0x00000001
2061 #define CP_EXEC_CS_1_NGROUPS_X__MASK				0xffffffff
2062 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT				0
CP_EXEC_CS_1_NGROUPS_X(uint32_t val)2063 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
2064 {
2065 	return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
2066 }
2067 
2068 #define REG_CP_EXEC_CS_2					0x00000002
2069 #define CP_EXEC_CS_2_NGROUPS_Y__MASK				0xffffffff
2070 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT				0
CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)2071 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
2072 {
2073 	return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
2074 }
2075 
2076 #define REG_CP_EXEC_CS_3					0x00000003
2077 #define CP_EXEC_CS_3_NGROUPS_Z__MASK				0xffffffff
2078 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT				0
CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)2079 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
2080 {
2081 	return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
2082 }
2083 
2084 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0				0x00000000
2085 
2086 
2087 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1				0x00000001
2088 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK			0xffffffff
2089 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT			0
A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)2090 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
2091 {
2092 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
2093 }
2094 
2095 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2				0x00000002
2096 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK		0x00000ffc
2097 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT		2
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)2098 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
2099 {
2100 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
2101 }
2102 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK		0x003ff000
2103 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT		12
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)2104 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
2105 {
2106 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
2107 }
2108 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK		0xffc00000
2109 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT		22
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)2110 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
2111 {
2112 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
2113 }
2114 
2115 
2116 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1				0x00000001
2117 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK		0xffffffff
2118 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT		0
A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)2119 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
2120 {
2121 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
2122 }
2123 
2124 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2				0x00000002
2125 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK		0xffffffff
2126 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT		0
A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)2127 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
2128 {
2129 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
2130 }
2131 
2132 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3				0x00000003
2133 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK		0x00000ffc
2134 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT		2
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)2135 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
2136 {
2137 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
2138 }
2139 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK		0x003ff000
2140 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT		12
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)2141 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
2142 {
2143 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
2144 }
2145 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK		0xffc00000
2146 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT		22
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)2147 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
2148 {
2149 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
2150 }
2151 
2152 #define REG_A6XX_CP_SET_MARKER_0				0x00000000
2153 #define A6XX_CP_SET_MARKER_0_MODE__MASK				0x000001ff
2154 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT			0
A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)2155 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)
2156 {
2157 	return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
2158 }
2159 #define A6XX_CP_SET_MARKER_0_MARKER__MASK			0x0000000f
2160 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT			0
A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)2161 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)
2162 {
2163 	return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
2164 }
2165 
REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0)2166 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2167 
REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0)2168 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2169 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK		0x00000007
2170 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT		0
A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)2171 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
2172 {
2173 	return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
2174 }
2175 
REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0)2176 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
2177 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK			0xffffffff
2178 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT			0
A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)2179 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
2180 {
2181 	return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
2182 }
2183 
REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0)2184 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
2185 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK			0xffffffff
2186 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT			0
A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)2187 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
2188 {
2189 	return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
2190 }
2191 
2192 #define REG_A6XX_CP_REG_TEST_0					0x00000000
2193 #define A6XX_CP_REG_TEST_0_REG__MASK				0x0003ffff
2194 #define A6XX_CP_REG_TEST_0_REG__SHIFT				0
A6XX_CP_REG_TEST_0_REG(uint32_t val)2195 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
2196 {
2197 	return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
2198 }
2199 #define A6XX_CP_REG_TEST_0_BIT__MASK				0x01f00000
2200 #define A6XX_CP_REG_TEST_0_BIT__SHIFT				20
A6XX_CP_REG_TEST_0_BIT(uint32_t val)2201 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
2202 {
2203 	return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
2204 }
2205 #define A6XX_CP_REG_TEST_0_WAIT_FOR_ME				0x02000000
2206 
2207 #define REG_CP_COND_REG_EXEC_0					0x00000000
2208 #define CP_COND_REG_EXEC_0_REG0__MASK				0x0003ffff
2209 #define CP_COND_REG_EXEC_0_REG0__SHIFT				0
CP_COND_REG_EXEC_0_REG0(uint32_t val)2210 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
2211 {
2212 	return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
2213 }
2214 #define CP_COND_REG_EXEC_0_BINNING				0x02000000
2215 #define CP_COND_REG_EXEC_0_GMEM					0x04000000
2216 #define CP_COND_REG_EXEC_0_SYSMEM				0x08000000
2217 #define CP_COND_REG_EXEC_0_MODE__MASK				0xf0000000
2218 #define CP_COND_REG_EXEC_0_MODE__SHIFT				28
CP_COND_REG_EXEC_0_MODE(enum compare_mode val)2219 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
2220 {
2221 	return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
2222 }
2223 
2224 #define REG_CP_COND_REG_EXEC_1					0x00000001
2225 #define CP_COND_REG_EXEC_1_DWORDS__MASK				0xffffffff
2226 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT			0
CP_COND_REG_EXEC_1_DWORDS(uint32_t val)2227 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2228 {
2229 	return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;
2230 }
2231 
2232 #define REG_CP_COND_EXEC_0					0x00000000
2233 #define CP_COND_EXEC_0_ADDR0_LO__MASK				0xffffffff
2234 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT				0
CP_COND_EXEC_0_ADDR0_LO(uint32_t val)2235 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
2236 {
2237 	return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
2238 }
2239 
2240 #define REG_CP_COND_EXEC_1					0x00000001
2241 #define CP_COND_EXEC_1_ADDR0_HI__MASK				0xffffffff
2242 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT				0
CP_COND_EXEC_1_ADDR0_HI(uint32_t val)2243 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
2244 {
2245 	return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
2246 }
2247 
2248 #define REG_CP_COND_EXEC_2					0x00000002
2249 #define CP_COND_EXEC_2_ADDR1_LO__MASK				0xffffffff
2250 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT				0
CP_COND_EXEC_2_ADDR1_LO(uint32_t val)2251 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
2252 {
2253 	return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
2254 }
2255 
2256 #define REG_CP_COND_EXEC_3					0x00000003
2257 #define CP_COND_EXEC_3_ADDR1_HI__MASK				0xffffffff
2258 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT				0
CP_COND_EXEC_3_ADDR1_HI(uint32_t val)2259 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
2260 {
2261 	return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
2262 }
2263 
2264 #define REG_CP_COND_EXEC_4					0x00000004
2265 #define CP_COND_EXEC_4_REF__MASK				0xffffffff
2266 #define CP_COND_EXEC_4_REF__SHIFT				0
CP_COND_EXEC_4_REF(uint32_t val)2267 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
2268 {
2269 	return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
2270 }
2271 
2272 #define REG_CP_COND_EXEC_5					0x00000005
2273 #define CP_COND_EXEC_5_DWORDS__MASK				0xffffffff
2274 #define CP_COND_EXEC_5_DWORDS__SHIFT				0
CP_COND_EXEC_5_DWORDS(uint32_t val)2275 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
2276 {
2277 	return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
2278 }
2279 
2280 #define REG_CP_SET_CTXSWITCH_IB_0				0x00000000
2281 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK			0xffffffff
2282 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT			0
CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)2283 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
2284 {
2285 	return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
2286 }
2287 
2288 #define REG_CP_SET_CTXSWITCH_IB_1				0x00000001
2289 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK			0xffffffff
2290 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT			0
CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)2291 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
2292 {
2293 	return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
2294 }
2295 
2296 #define REG_CP_SET_CTXSWITCH_IB_2				0x00000002
2297 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK			0x000fffff
2298 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT			0
CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)2299 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
2300 {
2301 	return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
2302 }
2303 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK			0x00300000
2304 #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT			20
CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)2305 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
2306 {
2307 	return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
2308 }
2309 
2310 #define REG_CP_REG_WRITE_0					0x00000000
2311 #define CP_REG_WRITE_0_TRACKER__MASK				0x00000007
2312 #define CP_REG_WRITE_0_TRACKER__SHIFT				0
CP_REG_WRITE_0_TRACKER(enum reg_tracker val)2313 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
2314 {
2315 	return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
2316 }
2317 
2318 #define REG_CP_SMMU_TABLE_UPDATE_0				0x00000000
2319 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK			0xffffffff
2320 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT			0
CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)2321 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
2322 {
2323 	return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
2324 }
2325 
2326 #define REG_CP_SMMU_TABLE_UPDATE_1				0x00000001
2327 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK			0x0000ffff
2328 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT			0
CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)2329 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
2330 {
2331 	return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
2332 }
2333 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK			0xffff0000
2334 #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT			16
CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)2335 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
2336 {
2337 	return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
2338 }
2339 
2340 #define REG_CP_SMMU_TABLE_UPDATE_2				0x00000002
2341 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK			0xffffffff
2342 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT		0
CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)2343 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
2344 {
2345 	return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
2346 }
2347 
2348 #define REG_CP_SMMU_TABLE_UPDATE_3				0x00000003
2349 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK		0xffffffff
2350 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT		0
CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)2351 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
2352 {
2353 	return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
2354 }
2355 
2356 #define REG_CP_START_BIN_BIN_COUNT				0x00000000
2357 
2358 #define REG_CP_START_BIN_PREFIX_ADDR				0x00000001
2359 
2360 #define REG_CP_START_BIN_PREFIX_DWORDS				0x00000003
2361 
2362 #define REG_CP_START_BIN_BODY_DWORDS				0x00000004
2363 
2364 
2365 #endif /* ADRENO_PM4_XML */
2366