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Searched refs:CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT (Results 1 – 11 of 11) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2887 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010 macro
Dgfx_7_2_sh_mask.h3158 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 macro
Dgfx_8_0_sh_mask.h3772 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 macro
Dgfx_8_1_sh_mask.h4294 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h1258 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … macro
Dgc_9_1_sh_mask.h1157 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … macro
Dgc_9_2_1_sh_mask.h1124 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … macro
Dgc_9_4_2_sh_mask.h1757 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … macro
Dgc_11_0_0_sh_mask.h6599 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … macro
Dgc_10_1_0_sh_mask.h6740 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … macro
Dgc_10_3_0_sh_mask.h7006 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT … macro