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Searched refs:CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK (Results 1 – 12 of 12) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2178 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2754 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L macro
Dgfx_7_2_sh_mask.h1091 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
Dgfx_8_0_sh_mask.h1407 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
Dgfx_8_1_sh_mask.h1931 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h10943 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_1_sh_mask.h12424 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_2_1_sh_mask.h12228 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_4_2_sh_mask.h2244 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_11_0_0_sh_mask.h15378 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_10_1_0_sh_mask.h17877 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_10_3_0_sh_mask.h16139 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK … macro